Embed Size (px)
Citation preview
US008209370B2
(12) Ulllted States Patent (10) Patent N0.: US 8,209,370 B2 Lablans (45) Date of Patent: *Jun. 26, 2012
(54) MULTI-VALUE DIGITAL CALCULATING 3,3 2 1i; glam?kawa 1 , , ontoye eta .
CIRCUITS, INCLUDING MULTIPLIERS 4,982,356 A M991 Ando
5,222,035 A 6/1993 Naka t l. (75) Inventor: Peter Lablans, Morris Township, N] 5227993 A 7/1993 yamaslfajvs
(US) 5,280,440 A 1/1994 Sugimura 5,289,399 A 2/1994 Yoshida
- , - - 5,379,245 A * 1/1995 Ueda ........................... .. 708/624 (73) Asslgnee. Ternaryloglc LLC, MornstoWn, NC 5,438,533 A 8/1995 Yoshida
(Us) 5,644,253 A 7/1997 Takatsu 6,535,902 B2 3/2003 Goto
( * ) Notice: Subject to any disclaimer, the term of this 6,567,835 B1 5/2003 Blomgren et a1. patent is extended or adjusted under 35 6,816,877 B2: 11/2004 Park et al' ~~~~~~~~~~~~~~~ " 708/628 U S C 154(1)) b 507 da S 7,562,106 B2 7/2009 Lablans ...................... .. 708/493
' ' ' y y ' 2001/0016864 A1 8/2001 Noeske
patent is subject IO a terminal (115 c a1mer.
Non-Final Of?ce Action in US. Appl. No. 12/267,900, mailed Sep.
(21) Appl. No.: 12/472,731 26, 2011, 6 PgS~ O. Sentieys et al. ‘Conception d’un processeur ternaire a faible
- . (e)nergie. (text in English)’, Colloque Faible Tension Faible (22) F?ed' May 27’ 2009 Consommation (FTFC ’03), 2003, 7 pages, Rennes, France.
_ _ _ C.S. Wallace; ‘A suggestion for a Fast Multiplier’ IEEE Trans. Elec
PI‘lOI‘ Publlcatlml Data tron‘ comput‘ Us 2009/0234900 A1 Sell 17 2009 R. Brent, H. Kung; ‘A regular lay-out for parallel adders.’ IEEE ’ Transactions on Computers C-31 (1982).
- - Gary W. Bewick; ‘Fast multiplication: algorithms and implementa Related U's' Apphcatlon Data tion.’ PhD. Thesis Stanford University. Feb. 1994. 170pg.
(63) Continuation of application No. 11/018,956, ?led on C t. d Dec. 20, 2004, noW Pat. No. 7,562,106. ( on “we )
(51) Int Cl Primary Examiner * Chuong D Ngo
Attorney, Agent, 0}’ i G06F 7/52 (2006.01)
(52) US. Cl. ...................................... .. 708/493; 708/620 (57) ABSTRACT
(58) Field of Classi?cation Search ................ .. 708/483, Apparatus and method for Performing multi-value arithmetic 708/620’ 623’ 624 operations are disclosed. Multi-Value signals can be added,
See application ?le for Complete Search history subtracted and multiplied using a ?rst truth table to generate a residue and a second truth table to generate a carry. Addi
(56) References Cited tionally, method and apparatus to ef?ciently perform the
US. PATENT DOCUMENTS
4,566,075 A 1/1986 Guttag 4,620,188 A 10/1986 Sengchanh 4,628,472 A 12/1986 Fensch
601 602
function a0b1+a1b0 on multi-Value signals are disclosed. Also an e?icient method of processing large binary signals is disclosed.
20 Claims, 34 Drawing Sheets
US 8,209,370 B2 Page 2
OTHER PUBLICATIONS
Kai Hwang. ‘Computer Arithmetic. Principles, Architecture, and Design.’ John Wiley & Sons 1979. pp. 84-91. Abraham Peled, Bede Liu. ‘Digital Signal Processing. Theory, Design and Implementation.’ Abraham Wiley and Sons 1976, p. 18.
J. Sklansky. ‘Conditional-Sum Addition Logic.’ IRE Transactions on Electronic Computers (1960). 0.]. Bedrij. ‘Carry-Select Adder’, IRE Trans. Electr. Comp. Jun. 1962, 340-346.
* cited by examiner
US. Patent Jun. 26, 2012 Sheet 1 0f 34 US 8,209,370 B2
‘I207
1204
\1211 (-1208 1202 1205
1215
‘I200
L
Figure 3
US. Patent Jun. 26, 2012 Sheet 2 0f 34
3001 3016 3007
\ k": 3009 3003
3000
\O é) \ 3011
3002 3005 3008
\_ \: 51,3012
3006 \ 3013
Figure 4
\ ‘301 0 3004
US 8,209,370 B2
3014
3015
US. Patent Jun. 26, 2012 Sheet 3 0f 34 US 8,209,370 B2
109 4f-102 l
/ / 104
106/
110 101 108
\107 103 —»C5
‘ \105 Figure 5
f 209
208 210
303
/ 304
\ 207
\ 205
Figure 7
n \J
/ 25 g) 203
F|gure6
201
US. Patent Jun. 26, 2012 Sheet 4 0f 34 US 8,209,370 B2
ARRANGE TWO 4x4 DIGITS NUMBERS 310 _' a3a2a1a0
b3b2b1 b0
311 _ a3a2a1a0 312 — a3a2a1a0
b1b0 b3b200
313
\ V V / GENERATE 5 RESIDUES (R) GENERATE 5 RESIDUES (R)
\ V V / GENERATE 5 FIRST GENERATE 5 FIRST
CARRIES (C) CARRIES (C)
315 319 \ v /
GENERATE 3 SECOND GENERATE 3 SECOND CARRIES (K) CARRIES (K)
i l / 320 316 "’ CSA R+C+K CSA R+C+K
321 —— CSA
CLA — 322
Figure 7A
US. Patent Jun. 26, 2012 Sheet 5 0f 34 US 8,209,370 B2
403
US. Patent Jun. 26, 2012 Sheet 6 0f 34 US 8,209,370 B2
1001 \
2
/ 1 004 1003
Figure 9
US. Patent Jun. 26, 2012 Sheet 7 0134 US 8,209,370 B2
501
\ ‘r502 504
Figure10
601 602
6030 6040 f f
607 6031 6041
Av’ r5’ 608 v \7
612 6032
M 446°” / 609 é, 1_ 603
6043 — M A’
610 2 i 6034
611 _d;/-— I605] A16044 606] 611 \Q/
Figure 11
US. Patent Jun. 26, 2012 Sheet 8 0f 34 US 8,209,370 B2
905
901 \ \r 909
907 & fa \ 910
902 903 —‘é
\_ r‘ 909
902‘ H: 906
Figure 12
US. Patent Jun. 26, 2012 Sheet 9 0f 34 US 8,209,370 B2
1401
1507
1400
\l
1513
1500
1604
1600
1610
1605
Figure 15
US. Patent Jun. 26, 2012 Sheet 10 0f 34 US 8,209,370 B2
1700
1 —\ 1713
170917101711 1712 Figure16
1801 1802 1803 1806
1803 / 1807 \ 1810 1 f 1 f AI W — w
1805 1804 1808 1809 1811 1812
1800 \ \ \ \ \ 1813
Figure 17
US. Patent Jun. 26, 2012 Sheet 11 0134 US 8,209,370 B2
701 702 703
\ \I 708 \ E 204
705 707 706 Figure ‘I8
820 808 X \ 802
O / k-/
803 1 80 Ah/
Figure 19
US. Patent Jun. 26, 2012 Sheet 12 0134 US 8,209,370 B2
3106 3107 3108
3101 x x \ > T _ _ _ _ _
T T > @109
3102 3103 3104 3105 E
Figure 20
3210 3106 3107 3108
3200 \3101 \ x \ \ T T _ _ _ _ _ T 0 3109
\ 3212 1 162) J’ 3105/ 3110
3102 3103 3104 > [I
V
Figure 20A 3211
US. Patent Jun. 26, 2012 Sheet 13 0f 34 US 8,209,370 B2
(1) a2
y(n)
Figure 208
US. Patent Jun. 26, 2012 Sheet 14 0f 34 US 8,209,370 B2
N- switch a b
source drain T o— —o T
gate 8
Figure 21 Figure 22
a b
a a 2 b
S = 0
Figure 23 S = 1
P- switch source drain
0— —o a b
gate Figure 24 _ 8
Figure 25
a b a b
. A . .—/L. S = 0 S = 1
US. Patent Jun. 26, 2012 Sheet 15 0f 34 US 8,209,370 B2
256
293
290 (J 298
291 \ / {J
299 (J 291 (J I {J
298 299
Figure 29
US. Patent Jun. 26, 2012 Sheet 16 0f 34 US 8,209,370 B2
296
297
301 y/ 299 292
291
302 294 303 304
Flgure 30
301 291 290 305
/ \ {j (J 302 W = 0 0 /
x r’ V 295
US. Patent Jun. 26, 2012 Sheet 17 0f 34 US 8,209,370 B2
Input Output_1
Latch Inverter Output 2 A _
V
Figure 32.
660
input_data / |0g_1
dock _ output_s _ |og_3
Latch
Q |og_2 output_r
Figure 33
US. Patent Jun. 26, 2012 Sheet 18 0f 34 US 8,209,370 B2
Input a b C d k I m n
I abcd efg h
k l m n
Figure 34
900 Input 0 1 2 j 0 1 2
I: m30 1 2 0 1 0
/ j 1 1 2 908 \ 901 2 2 2
904 f 905
Figure 35
Input 0 1 2 1 2 0 m31 2
|—— 0 1 0 1 2
2 0 1 1 2 0
2 0
Figure 36
![Ulllted States Patent [19] [11] Patent Number: 5,932,342€¦ · US005932342A Ulllted States Patent [19] [11] Patent Number: 5,932,342 Zeira et al. [45] Date of Patent: Aug. 3, 1999](https://img.dokumen.tips/doc/110x75/605be6553bed1b6a777c1449/ulllted-states-patent-19-11-patent-number-5932342-us005932342a-ulllted-states.jpg)
![Ulllted States Patent [19] [11] Patent Number: 6,138,105…US006138105A Ulllted States Patent [19] [11] Patent Number: 6,138,105 Walker et al. [45] Date of Patent: Oct. 24, 2000 [54]](https://img.dokumen.tips/doc/110x75/5b0c7a657f8b9a02508c3a7b/ulllted-states-patent-19-11-patent-number-6138105-ulllted-states-patent-19.jpg)
![Ulllted States Patent [19] [11] Patent Number: 5,970,479 · PDF fileUlllted States Patent [19] [11] Patent Number: 5,970,479 ... “The Game of Professional Investment is Intolerably](https://img.dokumen.tips/doc/110x75/5a7f2d0e7f8b9aee018b58f6/ulllted-states-patent-19-11-patent-number-5970479-states-patent-19-11.jpg)
