11 - Universidade do Estado de Santa Catarina · Disciplina: ELD0001 Gabarito da lista de exercícios 1 Joinville,20demarçode2016 6.Aindautilizandooresultadodoexercício4,utilizebuﬀers

Disciplina: ELD0001 Gabarito da lista de exercícios 1 Joinville, 20 de março de 2016

Curso de engenharia elétricaProfessor Renan Sebem

OBS: A resolução de alguns exercícios está escrita à mão no fim da lista.1. Escreva a equação para a função y implementada pelos circuitos (a) e (b) através de mosfets.

11.15 Exercises 1. Combinational × sequential logic

The circuit of Figure E11.1 is similar to that in Figure 11.1(c). Write the equation for y with the switch in position (1), then with it in position (2). Compare the two results. Is the fi rst circuit combinational and the second sequential? (Hint: If the function is combinational, the expression for y is nonrecur-sive, that is, y appears only on one side of the expression.)

2. Compound-gate #1

Write the equation for the function y implemented by each circuit of Figure E11.2 (note that one does not contain an inverter at the output).

3. Compound-gate #2

Draw the CMOS circuit for the following functions:

a. y = a + b · c + d · e · f

b. y = a · (b + c) · (d + e + f )

c. Are there any similarities between the resulting circuits?

4. Compound-gate #3

Consider the function y = a · b · c.

a. Draw its CMOS circuit using the SOP-based procedure described in Section 11.4, Figure 11.3(a).

b. Draw its CMOS circuit using the POS-based procedure described in Section 11.4, Figure 11.3(b). Draw it employing the equivalent equation y = (a + 0) · (b + 0) · (c + 0), and show that exactly the same circuit results as that in part (a) above.

11.15 Exercises 281

FIGURE E11.1.

FIGURE E11.2. a) OBS: A ordem das entradas está diferente da ordem utilizada em sala de aula, mas o resultado é omesmo!

Tabela verdade:Entradas Saída

D C B A Y0 0 0 0 10 0 0 1 10 0 1 0 10 0 1 1 10 1 0 0 10 1 0 1 10 1 1 0 10 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 01 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 0

Mapa de Karnaugh:

Y B A B A B A B A

D C 1 1 1 1D C 1 1 0 1D C 0 0 0 0D C 0 0 0 0

Equação:

Y = D ·B +D ·A+D · C

Y = D · (A+B + C)

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b)

Tabela verdade:Entradas SaídaC B A Y0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 1

Mapa de Karnaugh:

Y B A B A B A B A

C 0 1 1 1C 1 1 1 1

Equação:

Y = A+B + C

2. Escolha a quantidade de entradas, desenhe o símbolo de um codificador e um decodificador, identificandoas entradas e saídas.

3. Suponha que um chip de memória tem capacidade de 4 GB, dividida em 62,5 M palavras de 64 bits cada(ou seja 62500000 linhas). Qual o valor de N (número de entradas para este decodificador?

4. Projete e implemente, através de portas lógicas, um decodificador de endereço 3/8 conforme a tabela abaixo:

(a) Obtenha a espressão ótima para cada saída através do mapa de Karnaugh;

(b) Implemente o circuito utilizando apenas portas NAND, e inversores se necessário.

The circuit shown in Figure 11.8(b) is a direct implementation of the SOP expressions listed above using AND gates. In Figure 11.8(c), a CMOS architecture is depicted, which was obtained using the POS equations and the procedure described in Section 11.4 (notice that some of the transistors are shared between adjacent branches), thus resulting in a NOR gate in each column. In Figure 11.8(d), pseudo-nMOS logic was employed instead of CMOS, again based on the POS expressions (so each column is still a NOR gate). Finally, in Figure 11.8(e), footed dynamic logic was employed, and the implementation was based on the SOP expressions instead of POS, thus resulting in NAND gates in the columns (in this case, the dissimilar bit is low instead of high).

11.5 Encoders and Decoders 263

FIGURE 11.7. (a) Address decoder symbols; (b) Truth table for N = 3, with the dissimilar bit equal to '1' (“one-hot” code).

FIGURE 11.8. Address decoder implementations for N = 2: (a) Truth table; (b) SOP-based implementation with AND gates; (c) POS-based CMOS implementation (columns are NOR gates); (d) POS-based pseudo-nMOS implementation (again columns are NOR gates); (e) SOP-based footed dynamic implementation (columns are NAND gates). The dissimilar bit is high in all circuits except in (e).

The circuit shown in Figure 11.8(b) is a direct implementation of the SOP expressions listed above using AND gates. In Figure 11.8(c), a CMOS architecture is depicted, which was obtained using the POS equations and the procedure described in Section 11.4 (notice that some of the transistors are shared between adjacent branches), thus resulting in a NOR gate in each column. In Figure 11.8(d), pseudo-nMOS logic was employed instead of CMOS, again based on the POS expressions (so each column is still a NOR gate). Finally, in Figure 11.8(e), footed dynamic logic was employed, and the implementation was based on the SOP expressions instead of POS, thus resulting in NAND gates in the columns (in this case, the dissimilar bit is low instead of high).


FIGURE 11.7. (a) Address decoder symbols; (b) Truth table for N = 3, with the dissimilar bit equal to '1' (“one-hot” code).

FIGURE 11.8. Address decoder implementations for N = 2: (a) Truth table; (b) SOP-based implementation with AND gates; (c) POS-based CMOS implementation (columns are NOR gates); (d) POS-based pseudo-nMOS implementation (again columns are NOR gates); (e) SOP-based footed dynamic implementation (columns are NAND gates). The dissimilar bit is high in all circuits except in (e).

5. Sem modificar o circuito do exercício 4, adicione portas lógicas a fim de criar uma porta de enable para odecodificador como indica a figura abaixo.

Resolvido em sala de aula

11. Address decoder with enable #2

Similarly to the exercise above, but without modifying your solution to Exercise 11.9, introduce additional gates, as indicated in Figure E11.11, to allow the inclusion of an output-enable (ena) port, so the circuit operates as a regular decoder when ena = '1', or lowers all outputs when ena = '0'.

12. Address decoder with high-impedance output

Still regarding the address decoder of Figures E11.9 and E11.11, assume that now the enable port, when unasserted, must turn the outputs into a high-impedance state (see tri-state buffers in Section 4.8) instead of turning them low. Include the appropriate circuit for that to happen in the box marked with a question mark in Figure E11.11.

13. Address decoder with pseudo-nMOS logic

For the N = 3 address decoder of Figure E11.9, after obtaining the corresponding output equations, draw a NOR-type implementation using pseudo-nMOS logic (as in Figure 11.8(d)).

14. Address decoder with more inputs #1

Construct a 5-bit address decoder using only 3-bit address decoders.

11.15 Exercises 283

FIGURE E11.11.

FIGURE E11.14.



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6. Ainda utilizando o resultado do exercício 4, utilize buffers de terceiro estado para substituir o enable.


7. Construa um decodificador de 5 bits, utilizando apenas decodificadores de 3 bits com enable.


11. Address decoder with enable #2

Similarly to the exercise above, but without modifying your solution to Exercise 11.9, introduce additional gates, as indicated in Figure E11.11, to allow the inclusion of an output-enable (ena) port, so the circuit operates as a regular decoder when ena = '1', or lowers all outputs when ena = '0'.

12. Address decoder with high-impedance output

Still regarding the address decoder of Figures E11.9 and E11.11, assume that now the enable port, when unasserted, must turn the outputs into a high-impedance state (see tri-state buffers in Section 4.8) instead of turning them low. Include the appropriate circuit for that to happen in the box marked with a question mark in Figure E11.11.

13. Address decoder with pseudo-nMOS logic

For the N = 3 address decoder of Figure E11.9, after obtaining the corresponding output equations, draw a NOR-type implementation using pseudo-nMOS logic (as in Figure 11.8(d)).



11.15 Exercises 283

FIGURE E11.11.

FIGURE E11.14.



8. Para um codificador com N = 3:

O circuito está anexado no fim da lista.

(a) Escreva a tabela verdade;

(b) Escreva a expressão booleana ótima para cada saída;

(c) Desenhe o circuito.

Tabela verdade:Entradas Saídas

a7 a6 a5 a4 a3 a2 a1 a0 y2 y1 y0

0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1

Utilizando o mapa de Karnaugh as equações para y2, y1 e y0 resultariam em 4 minitermos de 8 variáveis.Este circuito não é ótimo pois sabe-se que apenas uma das entradas estará ativa por vez. Conhecendo estefato é possível projetar o circuito para as saídas através de portas OR, utilizando nas entradas as variáveisque estão em nível lógico ’1’ quando a saída projetada está em nível lógico ’1’:

y2 = a7 + a6 + a5 + a4

y1 = a7 + a6 + a3 + a2

y0 = a7 + a5 + a3 + a1

9. Projete através de portas lógicas, um codificador de prioridade 2/4 conforme a tabela abaixo:

Resolvido em laboratório

x y0001 000011 010111 101111 11

266 CHAPTER 11 Combinational Logic Circuits

SOLUTION

The solution is included in Figure 11.11. Note that, to make it easier to follow, plots for x1! and x0! were also included. As can be observed, only one output is high at a time. However, depending on the specifi c implementation and its propagation delays, glitches might occur during the transitions (which are generally acceptable in this type of circuit). ■

11.5.5 Address EncoderAn address encoder does precisely the opposite of what an address decoder does, that is, it converts a 2N-bit input that contains only one dissimilar bit into an N-bit output that encodes the position (address) of the dissimilar bit. Figure 11.12 shows three equivalent address encoder symbols plus the truth table for N = 2 and also an implementation example (for N = 2) using OR gates.

Many other parallel encoders/decoders exist besides the address encoder/decoder. An example is given below.

EXAMPLE 11.4 SSD DECODER

Figure 11.13(a) shows a seven-segment display (SSD), often used to display BCD-encoded numeric digits from 0 to 9 and also other characters. Two common technologies employed in their fabrication are LEDs (light emitting diodes) and LCD (liquid crystal display). The segments have one end in common, as illustrated for LED-based SSDs in Figures 11.13(b)–(c). In the common-cathode case, the cathode is

■

FIGURE 11.11. Timing diagram for a 2-bit address decoder implemented with conventional gates.

FIGURE 11.12. (a) Address encoder symbols; (b) Truth table for N = 2; (c) Implementation example with OR gates.

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10. Preencha a tabela e projete através de portas lógicas, um decodificador BCD/SSD (binary coded decimal/seven segment display): OBS: Escolha entre o display de cátodo comum ou ânodo comum.


normally connected to ground, so a segment is turned ON when the bit feeding it is '1'. In the common-anode confi guration, the anode is normally connected to VDD, so the opposite happens, that is, a seg-ment is turned ON when its corresponding bit is '0' (inverted logic). In this example, we are interested in using SSDs to display the output of a BCD counter (decimal digits from 0 to 9). Each digit is represented by 4 bits, while an SSD requires 7 bits to drive a digit (or 8 if the decimal point is also used). Therefore, a BCD-to-SSD converter (also called SSD driver or SSD decoder) is needed. A symbol for such a converter appears in Figure 11.13(d), and the corresponding truth table, for positive logic (that is, common-cathode) in Figure 11.13(e). Design a decoder to perform the BCD-to-SSD conversion. Recall that Karnaugh maps can be helpful to obtain an optimal (irreducible) SOP or POS expression for the segments (a, b, . . . , g).

SOLUTIONThe input bits are represented by ABCD in the truth table, and the output bits by abcdefg. For each output bit, a corresponding Karnaugh map is shown in Figure 11.14, from which we obtain the following equations:

a = A + C + B · D + B ! · D !

b = B ! + C · D + C ! · D !

c = (A ! · B ! · C · D !)!

d = A + B ! · C + B ! · D ! + C · D ! + B · C ! · D

e = B ! · D ! + C · D !

f = A + B · C ! + B · D ! + C ! · D !

g = A + B · C ! + B ! · C + C · D !

An AND-OR implementation for each of these expressions is shown along with the Karnaugh maps in Figure 11.14. Another implementation, using only NAND gates, is shown at the bottom of Figure 11.14.


FIGURE 11.13. (a) Seven-segment display (SSD); (b) Common-cathode confi guration; (c) Common-anode confi guration; (d) BCD-to-SSD converter symbol; (e) Truth table for common-cathode decoder.



a = A + C + B · D + B ! · D !

b = B ! + C · D + C ! · D !

c = (A ! · B ! · C · D !)!

d = A + B ! · C + B ! · D ! + C · D ! + B · C ! · D

e = B ! · D ! + C · D !

f = A + B · C ! + B · D ! + C ! · D !

g = A + B · C ! + B ! · C + C · D !






a = A + C + B · D + B ! · D !

b = B ! + C · D + C ! · D !

c = (A ! · B ! · C · D !)!

d = A + B ! · C + B ! · D ! + C · D ! + B · C ! · D

e = B ! · D ! + C · D !

f = A + B · C ! + B · D ! + C ! · D !

g = A + B · C ! + B ! · C + C · D !




Entrada Saída Cátodo comum Saída Ânodo Comum0000000100100011010001010110011110001001

11. Escolha a quantidade de entradas, desenhe o símbolo de um multiplexador e um demultiplexador, identifi-cando as entradas e saídas.

12. Desenhe o circuito de um multiplexador 4x1 utilizando somente portas NAND, e inversores se necessário.

Similar ao resolvido em laboratório

13. Desenhe o circuito de um demultiplexador 1x4.


14. Construa um multiplexador 8x1 utilizando apenas multiplexadores 4x1.

15. Adicione um buffer de terceiro estado na saída do multiplexador a fim de controlar a alta impedância naporta de saída y.

16. É possível formar um decodificador a partir de um demultiplexador? Como?

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11 - Universidade do Estado de Santa Catarina · Disciplina: ELD0001 Gabarito da lista de exercícios 1 Joinville,20demarçode2016 6.Aindautilizandooresultadodoexercício4,utilizebuﬀers