10/29/2004 EE 42 fall 2004 lecture 25 1

Lecture #25 Timing issues

10/29/2004 EE 42 fall 2004 lecture 25 2

Topics

Today:• Gate delays• Timing diagrams• Glitches

Reading: Handout

10/29/2004 EE 42 fall 2004 lecture 25 3

Alternative reading

Schwarz and Oldham

Electrical Engineering, an Introduction

Second edition

Saunders College publishing

Available used in campus bookstores

Recommended Chapters:

1-5Circuits

13,15transistors

11Digitial circuits

12Digital systems

10/29/2004 EE 42 fall 2004 lecture 25 4

Transistor Inverter ExampleIt may be simpler to just think of PMOS and NMOS transistors instead

of a general 3 terminal pull-up or pull-down devices or networks.

VIN-D

Pull-Down Network VOUT

IOUT

Output

VDD

Pull-Up Network

VIN-U

VIN-D

VIN-U

VOUT

IOUT

Output

VDD

p-type MOSTransistor(PMOS)

n-type MOSTransistor(NMOS)

10/29/2004 EE 42 fall 2004 lecture 25 5

Complementary Networks

• If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS.

• The reverse is also true.• Determining the logic function from CMOS circuit is

not hard:– Look at the NMOS half. It will tell you when the output is

logic zero.– Parallel transistors: “like or”– Series transistors: “like and”

10/29/2004 EE 42 fall 2004 lecture 25 6

Resistance and Capacitance

• The separation of charge by the oxide insulator creates a natural capacitance in the transistor from gate to source.

• The silicon through which ID flows has a natural resistance.

• There are other sources of capacitance and resistance too.

n-typemetal metaloxide insulator

metal

p-type

metal

gate

drain

n-type+ + + + + +

___

_

_ _

h hh h

- +

_ _ _

h

VGS > VTH(n)

h hh h h

e e e ee

10/29/2004 EE 42 fall 2004 lecture 25 7

Gate Delay

• Suppose VIN abruptly changed from logic 0 to logic 1.

• VOUT1 may not change quickly, since is attached to the gates of the next inverter.

• These gates must collect/discharge electrons to change voltage.• Each gate attached to the output contributes a capacitance.

D

S

VDD

D

S

VOUT1

D

S

VDD

D

S

VOUT2

VIN

e

e

10/29/2004 EE 42 fall 2004 lecture 25 8

Gate Delay—The Full Picture

• Where will these electrons come from/go to?• No charges can pass through the cutoff transistor.• Charges will go through the pull-down/pull-up transistors to

ground. These transistors contribute resistance.

D

S

VDD

D

S

VOUT1

D

S

VDD

D

S

VOUT2

VIN

e

e

10/29/2004 EE 42 fall 2004 lecture 25 9

Computing Gate Delay

1. Determine the capacitance of each gate attached to the output. These combine in parallel. Higher fan-out = more capacitance.

2. Determine which transistors are pulling-up or pulling-down the output. Each contributes a resistance, and may need to be combined in series and/or parallel.

3. The C from 1) and R from 2) are the RC for the VOUT1 transition.

D

S

VDD

D

S

VOUT1

D

S

VDD

D

S

VOUT2

VIN

tp = (ln 2)RC

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Example

• Suppose we have the following circuit:

• If A and B both transition from

logic 1 to logic 0 at t = 0,

find the voltage at the NAND

output, VOUT(t), for t ≥ 0.

A

B

Logic 0 = 0 V

Logic 1 = 1 V

NMOS resistance

Rn = 1 k

PMOS resistance

Rp = 2 k

Gate capacitance

CG = 50 pF

10/29/2004 EE 42 fall 2004 lecture 25 11

Answer• A and B both transition from 0 to 1. Since VOUT comes out of a NAND of

A with B, VOUT transitions from 1 to 0.

VOUT(0) = 1 V VOUT,f = 0 V

• Since the output is transitioning from 1 to 0, it is being pulled down. Both NMOS transistors in the NAND were previously cutoff, but are now active. The NMOS in the NAND are in series, so the resistances add:

R = 2 RN = 2 k

• The output in question feeds into 2 logic gate inputs (one inverter, one NOR). Each CMOS input is attached to two transistors. Thus we have 2 x 2 = 4 gate capacitances to charge. All capacitances are in parallel, so they add:

C = 4 CG = 200 pF

VOUT(t) = 0 + (1-0) e-t/(2 k 200 pF) V

VOUT(t) = e-t/(400 ns) V

10/29/2004 EE 42 fall 2004 lecture 25 12

Case #1: VIN = VDD = 5V

The Output is Pulled-Down

VOUT

IOUT

Output

VIN-D

VDD

VIN-U

p-type MOSTransistor(PMOS)

n-type MOSTransistor(NMOS)

VIN = VDD = 5V

The PMOS transistor is OFF when VIN > VDD-VTU

The NMOS transistor is ON when VIN > VTD

VOUT(V)0 3 5

IOUT(A)

20

60

100VIN = 5

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Case #2: VIN = 0 The Output is Pulled-Up

VOUT

IOUT

Output

VIN-D

VDD

VIN-U

p-type MOSTransistor(PMOS)

n-type MOSTransistor(NMOS)

VIN = 0VOUT(V)0 3 5

IOUT(A)

20

60

100 VIN=1V

The PMOS transistor is ON when VIN < VDD-VTU

The NMOS transistor is OFF when VIN < VTD

10/29/2004 EE 42 fall 2004 lecture 25 14

EFFECT OF GATE DELAY

Cascade of Logic Gates

AB

C

D

Inputs have different delays, but we ascribe a single worst-case delay to every gate

How many “gate delays for shortest path? ANSWER : 2

How many gate delays for longest path? ANSWER : 3

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Timing diagrams

• To show the time at which logic signals change, a timing diagram is used. For combinatorial logic, the diagram will just show gate delays and glitches

• AND gate:A

B

A•B

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C,B,A

D

)BA(

)(__

CB

B

D

t

t

t

t

t

Logic state

2

2

0

3

TIMING DIAGRAMS

Show transitions of variables vs time

AB

C

Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second.

)(__

CB

No change at t = 3

Note becomes valid one gate delay after B switches

B

1

0

Glitching: temporary switching to an incorrect value

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Inverter Propagation Delay

t = 0.69RDCOUT = 0.69(10k)(50fF) = 345 ps

Discharge (pull-down)

Discharge (pull-up)

t = 0.69RUCOUT = 0.69(10k)(50fF) = 345 ps

VOUT

VDD

VIN = Vdd

COUT = 50fF

VOUT

VDD

VIN = Vdd

RD

COUT = 50fF

10/29/2004 EE 42 fall 2004 lecture 25 18

CMOS Logic Gate

A

B

C

A

B C

VDD

VOUT

NMOS conduct when input is high.

PMOS only in pull-up

NMOS and PMOS use the same set of input signals

PMOS conduct when input is low

NMOS only in pull-down

NMOS conduct for A + (BC)

PMOS do not conduct when A +(BC)

Logic is Complementary and produces F = A + (BC)

10/29/2004 EE 42 fall 2004 lecture 25 19

CMOS Logic Gate: Example Inputs

A

B

C

A

B C

VDD

VOUT

NMOS do not conduct

Logic is Complementary and produces F = 1

A = 0B = 0C = 0

PMOS all conduct

Output is High

= VDD

10/29/2004 EE 42 fall 2004 lecture 25 20

CMOS Logic Gate: Example Inputs

A

B

C

A

B C

VDD

VOUT

NMOS B and C conduct; A open

Logic is Complementary and produces F = 0

A = 0B = 1C = 1

PMOS A conducts; B and C Open

Output is High

= 0

10/29/2004 EE 42 fall 2004 lecture 25 21

Switched Equivalent Resistance Network

A

B

C

A

B C

VDD

VOUT

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RDSwitches close when input is high.

Switches close when input is low.

10/29/2004 EE 42 fall 2004 lecture 25 22

Logic Gate Propagation Delay: Initial State

The initial state depends on the old (previous) inputs.

The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new (present) input state.

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RD

COUT = 50 fF

Example: A=0, B=0, C=0 for a long time.

These inputs provided a path to VDD

for a long time and the capacitor has precharged up to VDD = 5V.

10/29/2004 EE 42 fall 2004 lecture 25 23

Logic Gate Propagation Delay: Transient

At t=0, B and C switch from low to high (VDD) and A remains low.

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RD

COUT = 50 fF

COUT discharges through the pull-down resistance of gates B and C in series.

t = 0.69(RDB+RDC)COUT = 0.69(20k)(50fF) = 690 ps

The propagation delay is two times longer than that for the inverter!

This breaks the path from VOUT to VDD

And opens a path from VOUT to GND

10/29/2004 EE 42 fall 2004 lecture 25 24

Logic Gate: Worst Case Scenarios

What combination of previous and present logic inputs will make the Pull-Down the fastest?

What combination of previous and present logic inputs will make the Pull-Down the slowest?

What combination of previous and present logic inputs will make the Pull-Up the fastest?

What combination of previous and present logic inputs will make the Pull-Up the slowest?

Fastest overall?

Slowest overall?

AB

C

A

B C

VDD

VOUT

RU

RURU

RD

RD

RD

COUT = 50 fF

10/29/2004 EE 42 fall 2004 lecture 25 25

Logic Gate CascadeTo avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks.

B2 = VOUT 1

The four independent input are A1, B1, A2 and C2.

A2 high discharges gate 2 without even waiting for the output of gate 1.

C2 high and A2 low makes gate 2 wait for Gate 1 output

A2

B2

VDD

A1B1

A1

B1

VDD

VOUT 1

B2

C2

A2

C2 VOUT 2

50 fF 50 fF