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_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
100Mbps, 16-Channel LLTs
MA
X1
45
48
E/M
AX
14
54
8A
E
General DescriptionThe MAX14548E/MAX14548AE 16-channel, bidirectional level translators (LLTs) provide the level shifting neces-sary for 100Mbps data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a high-voltage logic signal on the VCC side of the device and vice versa.
The devices feature a programming frequency input (PF) that adjusts the one-shot accelerator on-time to guaran-tee a bit rate of 100Mbps with a load capacitance < 15pF and VL > 1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven low. The MAX14548E can drive capacitive loads up to 50pF with a guaranteed bit rate of 40Mbps when VL R 1.1V and PF is driven high. The MAX14548AE can drive capacitive loads up to 50pF with a guaranteed bit rate of 40Mbps when VL R 1.1V and PF is driven high.
The device operate at full speed with external drivers that source as low as 4mA output current. Each I/O chan-nel is pulled up to VCC or VL by an internal 35FA current source, allowing both devices to be driven by either push-pull or open-drain drivers.
The devices feature multiple power-saving features including an enable input (EN) that places the device into a low-power shutdown mode when driven low and an automatic shutdown mode that disables the part when VCC is less than VL. The MAX14548AE output driv-er is designed to operate at full speed (100Mbps) with VL > 1.4V, which reduces the dynamic supply current vs. the MAX14548E. The state of I/O VCC_and I/O VL_are in high-impedance state during shutdown.
The devices operate with VCC voltages from +1.7V to +3.6V and VL voltages from +1.1V to +3.6V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The devices are avail-able in a 40-bump WLP (2.16mm x 3.46mm) package with 0.4mm ball pitch, and operate over the extended -40NC to +85NC temperature range.
FeaturesS Bidirectional Level Translation
S 100Mbps Guaranteed Data Rate
S +1.7V to +3.6V Supply Voltage Range for VCC
S +1.1V to +3.6V Supply Voltage Range for VL (VCC > VL)
S -40NC to +85NC Extended Operating Temperature Range
ApplicationsCMOS Logic-Level Translation
Low-Voltage ASIC Level Translation
Smart Card Readers
Portable Communication Devices
Cell Phones
GPS
Telecommunications Equipment
19-5248; Rev 0; 4/10
Ordering Information/Selector Guide
Note: All devices operate over the -40°C to +85°C operating temperature range.+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit appears at end of data sheet.
EVALUATION KIT
AVAILABLE
PARTPIN-
PACKAGE
BIT RATE (PF = LOW)LOAD CAPACITANCE < 15pF
(Mbps)
BIT RATE (PF = HIGH)LOAD CAPACITANCE < 50pF
(Mbps)
LOW DYNAMIC SUPPLY
CURRENT
MAX14548EEWL+ 40 WLP 100 40 —
MAX14548AEEWL+ 40 WLP 100 40 Yes (VL > 1.1V)
100Mbps, 16-Channel LLTs
2
MA
X1
45
48
E/M
AX
14
54
8A
E
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)VCC, VL, EN, PF.......................................................-0.3V to +4VI/O VCC_ ................................................... -0.3V to (VCC + 0.3V)I/O VL_ ......................................................... -0.3V to (VL + 0.3V)Short-Circuit Duration I/O VL_, I/O VCC_ to GND ....................................................ContinuousContinuous Power Dissipation (TA = +70NC) 40-Bump WLP (derate 17.2mW/NC above +70NC) ....1379mW
Junction-to-Ambient Thermal Resistance (BJA) (Note 1) ........................................................................58NC/WOperating Temperature Range .......................... -40NC to +85NCStorage Temperature Range ............................ -65NC to +150NCJunction Temperature .....................................................+150NCSoldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, CVCC = 1FF, CVL = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
VL Supply Range VL 1.1 3.6 V
VCC Supply Range VCC 1.7 3.6 V
Supply Current from VCC IQVCC I/O VCC_ = VCC, I/O VL_ = VL 40 FA
Supply Current from VL IQVL I/O VCC_ = VCC, I/O VL_ = VL 20 FA
VCC Shutdown Supply Current
ISHDN-VCCTA = +25NC, EN = GND, unconnected I/O pins
0.1 1 FA
VL Shutdown Mode Supply Current
ISHDN-VL
TA = +25NC, EN = GND, unconnected I/O pins
0.1 1
FATA = +25NC, EN = VL, VCC = GND, unconnected I/O pins
0.1 2
Dynamic Supply Current ID
One I/O switching at 25MHz; all other I/O connected to VCC or VL; CLOAD = 0pF
MAX14548E 2.9
mA
MAX14548AE 2.6
I/O VCC_, I/O VL_ Three-State Leakage Current
ILEAK TA = +25NC, EN = GND 0.1 6 FA
EN, PF Input Leakage Current ILEAK_EN_PF TA = +25NC 1 FA
VL Shutdown Threshold VTH_VL 0.3 V
VL - VCC Shutdown Threshold High
VTH_H VCC rising (VL = 3.6V) (Note 4) 0.05 0.3 0.65 V
VL - VCC Shutdown Threshold Low
VTH_L VCC falling (VL = 3.6V) (Note 4) 0.2 0.52 0.85 V
I/O VL_ Pullup Current IVL_PU_ I/O VL_ = GND, I/O VCC_ = GND 10 125 FA
I/O VCC_ Pullup Current IVCC_PU_ I/O VCC_ = GND, I/O VL_ = GND 15 90 FA
I/O VL_ to I/O VCC_ DC Resistance
RIOVL_IOVCC (Note 5) 3 kI
100Mbps, 16-Channel LLTs
3
MA
X1
45
48
E/M
AX
14
54
8A
E
ELECTRICAL CHARACTERISTICS (continued)(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, CVCC = 1FF, CVL = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ESD PROTECTION
I/O VCC_, I/O VL_
Human Body Model, CVCC = 1FF, CVL = 1FF
Unpowered device
Q12kV
Powered device Q5
All Other Pins Q2 kV
LOGIC LEVELS
I/O VL_ Input-Voltage High Threshold
VIHL (Note 6)VL - 0.2
V
I/O VL_ Input-Voltage Low Threshold
VILL (Note 6) 0.15 V
I/O VCC_ Input-Voltage High Threshold
VIHC (Note 6)VCC - 0.4
V
I/O VCC_ Input-Voltage Low Threshold
VILC (Note 6) 0.2 V
EN, PF Input-Voltage High Threshold
VIH
1.1V < VL < 1.3VVL - 0.25
VVL = 1.8V
VL - 0.4
EN, PF Input-Voltage Low Threshold
VIL1.1V < VL < 1.3V 0.4
VVL = 1.8V 0.4
I/O VL_ Output-Voltage High VOHL I/O VL_ source current = 10FA4/5 x VL
V
I/O VL_ Output-Voltage Low, Drop to GND
VOLLI/O VL_ sink current = 20FA, I/O VCC_ < 0.05V
1/3 x VL
V
I/O VCC_ Output-Voltage High VOHC I/O VCC_ source current = 10FA4/5 x VCC
V
I/O VCC_ Output-Voltage Low, Drop to GND
VOLCI/O VCC_ sink current = 20FA, I/O VL_ < 0.05V
1/3 x VCC
V
RISE/FALL TIME ACCELERATOR STAGE
Accelerator Pulse Duration
PF = lowOn rising edge 2.65
nsOn falling edge 2.5
PF = highOn rising edge 4
nsOn falling edge 3.7
VL Output Accelerator Source Impedance
VL = 1.62V 7I
VL = 3.2V 4.43
VCC Output Accelerator Source Impedance
VCC = 2.2V 14.2I
VCC = 3.6V 11.2
VL Output Accelerator Sink Impedance
VL = 1.62V 15.3I
VL = 3.2V 15.3
VCC Output Accelerator Sink Impedance
VCC = 2.2V 20.3I
VCC = 3.6V 19.5
100Mbps, 16-Channel LLTs
4
MA
X1
45
48
E/M
AX
14
54
8A
E HIGH-SPEED TIMING CHARACTERISTICS—MAX14548E(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = low, CVCC = 1FF, CVL = 1FF, CIOVL P 15pF, CIOVCC P 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
HIGH-SPEED TIMING CHARACTERISTICS—MAX14548AE(VCC = +1.7V to +3.6V, VL = +1.4V to +3.6V, VCC > VL, EN = VL, PF = low, CVCC = 1FF, CVL = 1FF, CIOVL P 15pF, CIOVCC P 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O VCC_ Rise Time tRVCC Input rise time < 2ns, Figure 1 2 ns
I/O VCC_ Fall Time tFVCC Input fall time < 2ns, Figure 1 2 ns
I/O VL_ Rise Time tRVL Input rise time < 2ns, Figure 2 2 ns
I/O VL_ Fall Time tFVL Input fall time < 2ns, Figure 2 2 ns
Propagation Delay (Driving I/O VL_)
tPVL-VCC Input rise time < 2ns, Figure 1 2.75 ns
Propagation Delay (Driving I/O VCC_)
tPVCC-VL Input rise time < 2ns, Figure 2 2.26 ns
Channel-to-Channel Skew tSKEW Input rise time/fall time < 2ns 0.2 ns
Propagation Delay from I/O VL_ to I/O VCC_ After EN
tEN-VCC RLOAD = 1MI, Figure 3 27 Fs
Propagation Delay from I/O VCC_ to I/O VL_ After EN
tEN-VL RLOAD = 1MI, Figure 3 0.05 Fs
Maximum Data RatePush-pull operation 100
MbpsOpen-drain operation 0.3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O VCC_ Rise Time tRVCC Input rise time < 2ns, Figure 1 2 ns
I/O VCC_ Fall Time tFVCC Input fall time < 2ns, Figure 1 2 ns
I/O VL_ Rise Time tRVL Input rise time < 2ns, Figure 2 2 ns
I/O VL_ Fall Time tFVL Input rise time < 2ns, Figure 2 2 ns
Propagation Delay (Driving I/O VL_)
tPVL-VCC Input rise time < 2ns, Figure 1 2.75 ns
Propagation Delay (Driving I/O VCC_)
tPVCC-VL Input rise time < 2ns, Figure 2 2.26 ns
Channel-to-Channel Skew tSKEW Input rise time/fall time < 2ns 0.2 ns
Propagation Delay from I/O VL_ to I/O VCC_ After EN
tEN-VCC RLOAD = 1MI, Figure 3 27 Fs
Propagation Delay from I/O VCC_ to I/O VL_ After EN
tEN-VL RLOAD = 1MI, Figure 3 0.05 Fs
Maximum Data RatePush-pull operation 100
MbpsOpen-drain operation 0.3
100Mbps, 16-Channel LLTs
5
MA
X1
45
48
E/M
AX
14
54
8A
E
LOW-SPEED TIMING CHARACTERISTICS—MAX14548E(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
LOW-SPEED TIMING CHARACTERISTICS—MAX14548AE(VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3)
Note 2: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and not production tested.
Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and shutdown conditions.
Note 4: When VCC is below VL by more than the VL - VCC shutdown threshold, the device turns off its pullup generators and I/O VCC_ and I/O VL_ enter their respective shutdown states.
Note 5: Guaranteed by design.Note 6: Input thresholds are referenced to the boost circuit.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O VCC_ Rise Time tRVCC Input rise time < 6ns, Figure 1 6 ns
I/O VCC_ Fall Time tFVCC Input fall time < 6ns, Figure 1 6 ns
I/O VL_ Rise Time tRVL Input rise time < 6ns, Figure 2 6 ns
I/O VL_ Fall Time tFVL Input rise time < 6ns, Figure 2 6 ns
Propagation Delay (Driving I/O VL_)
tPVL-VCC Input rise time < 6ns, Figure 1 4 ns
Propagation Delay (Driving I/O VCC_)
tPVCC-VL Input rise time < 6ns, Figure 2 3.37 ns
Channel-to-Channel Skew tSKEW Input rise time/fall time < 6ns 0.2 0.5 ns
Propagation Delay from I/O VL_ to I/O VCC_ After EN
tEN-VCC RLOAD = 1MI, Figure 3 27 Fs
Propagation Delay from I/O VCC_ to I/O VL_ After EN
tEN-VL RLOAD = 1MI, Figure 3 0.06 Fs
Maximum Data RatePush-pull operation 40
MbpsOpen-drain operation 0.3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O VCC_ Rise Time tRVCC Input rise time < 6ns, Figure 1 6 ns
I/O VCC_ Fall Time tFVCC Input fall time < 6ns, Figure 1 6 ns
I/O VL_ Rise Time tRVL Input rise time < 6ns, Figure 2 6 ns
I/O VL_ Fall Time tFVL Input rise time < 6ns, Figure 2 6 ns
Propagation Delay (Driving I/O VL_)
tPVL-VCC Input rise time < 6ns, Figure 1 4 ns
Propagation Delay (Driving I/O VCC_)
tPVCC-VL Input rise time < 6ns, Figure 2 3.37 ns
Channel-to-Channel Skew tSKEW Input rise time/fall time < 6ns 0.2 ns
Propagation Delay from I/O VL_ to I/O VCC_ After EN
tEN-VCC RLOAD = 1MI, Figure 3 27 Fs
Propagation Delay from I/O VCC_ to I/O VL_ After EN
tEN-VL RLOAD = 1MI, Figure 3 0.06 Fs
Maximum Data RatePush-pull operation 40
MbpsOpen-drain operation 0.3
100Mbps, 16-Channel LLTs
6
MA
X1
45
48
E/M
AX
14
54
8A
E
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
Figure 2. Push-Pull Driving I/O VCC_ Test Circuit and Timing
MAX14548EMAX14548AE
VL
VL
VL
I/O VL_ I/O VCC_
CIOVCC
VCC
VCC
EN
I/O VL_
I/O VCC_ 10%
50%
50%
90%
tRVCC
tPLH
tPVL-VCC = tPLH OR tPHL
tPLH
10%
50%
50%
90%
tFVCC
NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED.
VCC
MAX14548EMAX14548AE
VL
VL
I/O VL_ I/O VCC_
I/O VL_
I/O VCC_VCC
VCC
EN
CIOVCC
50%
10%
50%
90%50% 90%
10%
50%
tPLH tPLH
tPVCC-VL = tPLH OR tPHL
tRVL tFVL
NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED.
VL VCC
100Mbps, 16-Channel LLTs
7
MA
X1
45
48
E/M
AX
14
54
8A
E
Figure 3. Enable Test and Timing
MAX14548EMAX14548AE
EN
I/O VL_
RLOAD CIOVCC
I/O VCC_SOURCE
VL
EN
VL
VCC
VL
O
O
OI/O VCC_ VCC/2
t’EN-VCC
I/O VL_
MAX14548EMAX14548AE
EN
RLOADCIOVL VCC
I/O VCC_
SOURCEI/O VL_
I/O VL_
VCC
VL
O
O
O
I/O VCC_
VL /2
EN
VL
t’EN-VL
MAX14548EMAX14548AE
EN
I/O VL_
RLOAD
CIOVCC
I/O VCC_
SOURCE
VCC
VCC
VL
O
O
O
I/O VCC_VCC/2
I/O VL_
EN
VL
t”EN-VCC
tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
MAX14548EMAX14548AE
EN
RLOAD
CIOVL
VL
I/O VCC_
SOURCE
I/O VL_
tEN-VL IS WHICHEVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL.
I/O VL_
VL
VCC
VL
O
O
O
I/O VCC_
VL /2
ENt”EN-VL
VL VCC
VL VCC
VL VCC
VL VCC
100Mbps, 16-Channel LLTs
8
MA
X1
45
48
E/M
AX
14
54
8A
E Typical Operating Characteristics(VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.)
RISE TIME vs. CAPACITIVE LOADON I/O VL (DRIVING ONE I/O VCC)
MAX
1454
8E to
c09
RISE
TIM
E (n
s)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
CAPACITIVE LOAD (pF)
40302010 50
DATA RATE = 40Mbps
tFVLMAX14548AE (PF HIGH)
tRVLMAX14548AE (PF LOW)
tFVLMAX14548E(PF HIGH)
tRVLMAX14548E (PF LOW)
FALL TIME vs. CAPACITIVE LOADON I/O VCC (DRIVING ONE I/O VL)
MAX
1454
8E to
c08
CAPACITIVE LOAD (pF)
FALL
TIM
E (n
s)
403020
0.5
1.0
1.5
2.0
2.5
010 50
tFVCC MAX14548AE (PF HIGH)
tRVCC MAX14548AE (PF LOW)
tRVCC MAX14548E
(PF LOW)
tFVCC MAX14548E(PF HIGH)
DATA RATE = 40Mbps
RISE TIME vs. CAPACITIVE LOADON I/O VCC (DRIVING ONE I/O VL)
MAX
1454
8E to
c07
CAPACITIVE LOAD (pF)
RISE
TIM
E (n
s)
403020
0.5
1.0
1.5
2.0
2.5
010 50
tFVCC MAX14548AE (PF HIGH)
tFVCC MAX14548E (PF HIGH)
tRVCC MAX14548AE
(PF LOW)
tRVCC MAX14548E
(PF LOW)
DATA RATE = 40Mbps
VCC SUPPLY CURRENT vs. CAPACITIVELOAD (DRIVING ONE I/O VL_)
MAX
1454
8E to
c06
V L S
UPPL
Y CU
RREN
T (µ
A)
500
1000
1500
2000
2500
3000
3500
0
CAPACITIVE LOAD (pF)
40302010 50
MAX14548EPF LOW
MAX14548AEPF LOW
DATA RATE = 40Mbps
MAX14548AEPF HIGH
MAX14548EPF HIGH
VL SUPPLY CURRENT vs. CAPACITIVE LOAD(DRIVING ONE I/O VCC)
V L S
UPPL
Y CU
RREN
T (µ
A)
200
400
600
800
1000
1200
1400
1600
1800
0
MAX
1454
8E to
c05
CAPACITIVE LOAD (pF)
40302010 50
DATA RATE = 40Mbps
MAX14548EPF LOW
MAX14548AEPF HIGH
MAX14548EPF HIGH
MAX14548AEPF LOW
VCC SUPPLY CURRENT vs. VL SUPPLYVOLTAGE (DRIVING ONE I/O VCC_)
MAX
1454
8E to
c04
VL SUPPLY VOLTAGE (V)
3.12.62.11.61.1 3.6
MAX14548AE
MAX14548E
VCC = 3.6VCLOAD = 15pFPF = HIGHDATA RATE = 40Mbps
V CC
SUPP
LY C
URRE
NT (m
A)
1
2
3
4
5
6
7
0
VCC SUPPLY CURRENT vs. VCC SUPPLYVOLTAGE (DRIVING ONE I/O VL_)
MAX
1454
8E to
c03
V CC
SUPP
LY C
URRE
NT (m
A)
1
2
3
4
5
6
7
0
VCC SUPPLY VOLTAGE (V)
3.1252.6502.1751.700 3.600
MAX14548E
MAX14548AE
CLOAD = 15pFPF = HIGHDATA RATE = 40Mbps
V CC
SUPP
LY C
URRE
NT (m
A)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
MAX
1454
8E to
c02
VL SUPPLY VOLTAGE (V)
1.6 2.1 2.6 3.11.1 3.6
VCC SUPPLY CURRENT vs. VL SUPPLYVOLTAGE (DRIVING ONE I/O VCC_)
VCC = 3.6VCLOAD = 15pFPF = LOWDATA RATE = 40Mbps
MAX14548AE
MAX14548E
VL SUPPLY CURRENT vs. VCC SUPPLYVOLTAGE (DRIVING ONE I/O VL_)
MAX
1454
8E to
c01
VCC SUPPLY VOLTAGE (V)
V L S
UPPL
Y CU
RREN
T (µ
A)
3.1252.6502.175
50
100
150
200
250
01.700 3.600
MAX14548E
MAX14548AE
CLOAD = 15pFPF = LOW
100Mbps, 16-Channel LLTs
9
MA
X1
45
48
E/M
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8A
E
Typical Operating Characteristics (continued)(VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.)
TYPICAL I/O VCC_ DRIVING(DATA RATE = 100Mbps, CIOVL = 10pF),
PF = LOW, MAX14548EMAX14548E toc15
I/O VCC1V/div
I/O VL1V/div
10ns/div
TYPICAL I/O VL_ DRIVING(DATA RATE = 40Mbps, CIOVCC = 47pF),
PF = HIGH, MAX14548EMAX14548E toc14
I/O VL1V/div
I/O VCC1V/div
20ns/div
TYPICAL I/O VL_ DRIVING(DATA RATE = 100Mbps, CIOVCC = 10pF),
PF = LOW, MAX14548EMAX14548E toc13
I/O VL1V/div
I/O VCC1V/div
10ns/div
PROPAGATION DELAY vs. CAPACITIVE LOADON I/O VL (DRIVING ONE I/O VCC)
PROP
AGAT
ION
DELA
Y (n
s)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
MAX
1454
8E to
c12
CAPACITIVE LOAD (pF)
40302010 50
DATA RATE = 40Mbps
tPVCC-VL MAX14548E(PF HIGH)
tPVCC-VL MAX14548E
(PF LOW)
tPVCC-VL MAX14548AE
(PF LOW)
tPVCC-VLMAX14548AE
(PF HIGH)
PROPAGATION DELAY vs. CAPACITIVELOAD ON I/O VCC (DRIVING ONE I/O VL)
MAX
1454
8E to
c11
PROP
AGAT
ION
DELA
Y (n
s)0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0DATA RATE = 40Mbps
CAPACITIVE LOAD (pF)
40302010 50
tPVL-VCC MAX14548E
(PF LOW)
tPVL-VCC MAX14548AE
(PF LOW)
tPVL-VCC MAX14548E(PF HIGH)
tPVL-VCC MAX14548AE
(PF HIGH)
FALL TIME vs. CAPACITIVE LOADON I/O VL (DRIVING ONE I/O VCC)
MAX
1454
8E to
c10
CAPACITIVE LOAD (pF)
FALL
TIM
E (n
s)
403020
0.5
1.0
1.5
2.0
2.5
010 50
tFVLMAX14548AE (PF HIGH)
tFVL MAX14548E (PF HIGH)
tRVL MAX14548AE
(PF LOW)
tRVL MAX14548E
(PF LOW)
DATA RATE = 40Mbps
100Mbps, 16-Channel LLTs
10
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E Typical Operating Characteristics (continued)(VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.)
TYPICAL I/O VCC_ DRIVING(DATA RATE = 40Mbps, CIOVL = 47pF),
PF = HIGH, MAX14548AEMAX14548E toc20
I/O VCC1V/div
I/O VL1V/div
20ns/div
TYPICAL I/O VCC_ DRIVING(DATA RATE = 100Mbps, CIOVL = 10pF),
PF = LOW, MAX14548AEMAX14548E toc19
I/O VCC1V/div
I/O VL1V/div
10ns/div
TYPICAL I/O VL_ DRIVING(DATA RATE = 40Mbps, CIOVCC = 47pF),
PF = HIGH, MAX14548AEMAX14548E toc18
I/O VL1V/div
I/O VCC1V/div
20ns/div
TYPICAL I/O VL_ DRIVING(DATA RATE = 100Mbps, CIOVCC = 10pF),
PF = LOW, MAX14548AEMAX14548E toc17
I/O VL1V/div
I/O VCC1V/div
10ns/div
TYPICAL I/O VCC_ DRIVING(DATA RATE = 40Mbps, CIOVL = 47pF),
PF = HIGH, MAX14548EMAX14548E toc16
I/O VCC1V/div
I/O VL1V/div
20ns/div
100Mbps, 16-Channel LLTs
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Pin Configuration
Pin Description
TOP VIEW(BUMPS ON BOTTOM)
1
A
B
C
D
2 3 4
WLP(2.16mm × 3.46mm)
E
5 6 7 8
I/O VL4I/O VL3I/O VL2I/O VL1 I/O VL8I/O VL7I/O VL6I/O VL5
I/O VL12I/O VL11I/O VL10I/O VL9 I/O VL16I/O VL15I/O VL14I/O VL13
ENVCCVLGND GNDVLVCCPF
I/O VCC4I/O VCC3I/O VCC2I/O VCC1 I/O VCC8I/O VCC7I/O VCC6I/O VCC5
I/O VCC12I/O VCC11I/O VCC10I/O VCC9 I/O VCC16I/O VCC15I/O VCC14I/O VCC13
MAX14548EMAX14548AE
+
PIN NAME FUNCTION
A1 I/O VL1 Input/Output 1. Referenced to VL.
A2 I/O VL2 Input/Output 2. Referenced to VL.
A3 I/O VL3 Input/Output 3. Referenced to VL.
A4 I/O VL4 Input/Output 4. Referenced to VL.
A5 I/O VL5 Input/Output 5. Referenced to VL.
A6 I/O VL6 Input/Output 6. Referenced to VL.
A7 I/O VL7 Input/Output 7. Referenced to VL.
A8 I/O VL8 Input/Output 8. Referenced to VL.
B1 I/O VL9 Input/Output 9. Referenced to VL.
B2 I/O VL10 Input/Output 10. Referenced to VL.
B3 I/O VL11 Input/Output 11. Referenced to VL.
B4 I/O VL12 Input/Output 12. Referenced to VL.
B5 I/O VL13 Input/Output 13. Referenced to VL.
B6 I/O VL14 Input/Output 14. Referenced to VL.
B7 I/O VL15 Input/Output 15. Referenced to VL.
B8 I/O VL16 Input/Output 16. Referenced to VL.
C1, C8 GND Ground
100Mbps, 16-Channel LLTs
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E Pin Description (continued)PIN NAME FUNCTION
C2, C7 VLLogic Supply Voltage, +1.1V to +3.6V. Bypass VL to GND with a 1FF capacitor placed as close as possible to the device.
C3, C6 VCC
Power-Supply Voltage, +1.7V to +3.6V. Bypass VCC to GND with a 0.1FF ceramic capacitor. For full ESD protection, connect an additional 1FF ceramic capacitor from VCC to GND as close as possible to the VCC input.
C4 EN Enable Input. Drive EN to GND for shutdown mode, or drive EN to VL or VCC for normal operation.
C5 PFProgrammable Frequency Input. Drive PF low for high-frequency operation. Drive PF high for lower frequency operation.
D1 I/O VCC1 Input/Output 1. Referenced to VCC.
D2 I/O VCC2 Input/Output 2. Referenced to VCC.
D3 I/O VCC3 Input/Output 3. Referenced to VCC.
D4 I/O VCC4 Input/Output 4. Referenced to VCC.
D5 I/O VCC5 Input/Output 5. Referenced to VCC.
D6 I/O VCC6 Input/Output 6. Referenced to VCC.
D7 I/O VCC7 Input/Output 7. Referenced to VCC.
D8 I/O VCC8 Input/Output 8. Referenced to VCC.
E1 I/O VCC9 Input/Output 9. Referenced to VCC.
E2 I/O VCC10 Input/Output 10. Referenced to VCC.
E3 I/O VCC11 Input/Output 11. Referenced to VCC.
E4 I/O VCC12 Input/Output 12. Referenced to VCC.
E5 I/O VCC13 Input/Output 13. Referenced to VCC.
E6 I/O VCC14 Input/Output 14. Referenced to VCC.
E7 I/O VCC15 Input/Output 15. Referenced to VCC.
E8 I/O VCC16 Input/Output 16. Referenced to VCC.
100Mbps, 16-Channel LLTs
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Functional Diagram
Detailed DescriptionThe MAX14548E/MAX14548AE 16-channel, bidirectional level translators (LLTs) provide the level shifting neces-sary for 100Mbps data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a high-voltage logic signal on the VCC side of the device and vice versa.
The devices operate at full speed with external drivers that source as little as 4mA output current (min). Each I/O channel is pulled up to VCC or VL by an internal 35FA current source, allowing the devices to be driven by either push-pull or open-drain drivers.
The devices feature an enable input (EN) that places the device into a low-power shutdown mode when driven low. They also feature an automatic shutdown mode that disables the part when VCC is less than VL.
The devices feature a programmable frequency input (PF) that guarantees a bit rate of 100Mbps with a load capacitance < 15pF and VL > 1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven low. The MAX14548E can drive capacitive loads up to 50pF with a guaranteed bit rate of 40Mbps when VL R 1.1V and PF is driven high. The MAX14548AE can drive capacitive loads up to 50pF with a guaranteed bit rate of 40Mbps when VL R 1.1V and PF is driven high.
Level TranslationFor proper operation, ensure that 1.7V P VCC P 3.6V, 1.1V P VL P VCC. When power is supplied to VL while VCC is less than VL, the devices automatically enter a low-power mode and the I/Os are in high-impedance mode. The devices also enter shutdown mode when EN = 0. In both conditions where EN = 0 or VL > VCC, there is a known high-impedance state on I/O VL_and I/O VCC_. The maximum data rate depends heavily on the load capacitance (see the rise/fall time graphs in the Typical Operating Characteristics), output impedance of the driver, and the operating voltage range.
Input Driver RequirementsThe device architecture is based on an nMOS pass gate and output accelerator stages (Figure 4). The accelera-tors are active only when there is a rising/falling edge on a given I/O. A short pulse is then generated where the output accelerator stages become active and charge/discharge the capacitances at the I/Os. Due to its archi-tecture, both input stages become active during the one-shot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps speed up the transition on the driven side.
The devices have internal current sources capable of sourcing 35FA to pull up the I/O lines. These internal pullup current sources allow the inputs to be driven with open-drain drivers and push-pull drivers. It is not recom-mended to use external pullup resistors on the I/O lines. The architecture of the devices permit either side to be driven with a minimum of 4mA drivers or larger.
Output Load RequirementsThe device I/Os are designed to drive CMOS inputs. Do not load the I/O lines with a resistive load less than 25kI and do not place an RC circuit at the input of these devices to slow down the edges. If a slower rise/fall time is required, refer to the MAX3000E/MAX3001E/MAX3002–MAX3012 data sheet.
MAX14548EMAX14548AE
VL
I/O VL1
I/O VL2
I/O VL15
I/O VL16
EN
PF
GND
I/O VCC1
I/O VCC2
I/O VCC15
I/O VCC16
VCC
100Mbps, 16-Channel LLTs
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Shutdown ModeThe EN input places the devices into a low-power shut-down mode when driven low. The automatic shutdown mode disables the devices when VCC is unconnected or less than VL. When VCC is less than VL or EN = GND, the devices enter shutdown mode.
Data Rate and Capacitive Load (PF Input)The programmable frequency input (PF) adjusts the one-shot accelerator to guarantee a 100Mbps bit rate with a load capacitance <15pF and VL > 1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven low. The MAX14548E can drive capacitive loads up to 50pF with a guaranteed 40Mbps bit rate when VL > 1.1V and PF is driven high. The MAX14548AE can drive capacitive loads up to 50pF with a guaranteed 40Mbps bit rate when VL > 1.1V and PF is driven high.
Applications InformationLayout Recommendations
Use standard high-speed layout practices when laying out a board with the MAX14548E/MAX14548AE. For example, to minimize line coupling, place all other signal lines not connected to the devices at least 1x the sub-strate height of the PCB away from the input and output lines of the devices.
Power-Supply DecouplingTo reduce ripple and the chance of introducing data errors, bypass VL and VCC to ground with 0.1FF ceramic capacitors. Place all capacitors as close as possible to the power-supply inputs. For full ESD protection, bypass VCC with a 1FF ceramic capacitor located as close as possible to the VCC input.
Figure 4. Simplified Functional Diagram for One I/O Line
30µA
VL
ENABLE
ENABLE
ENABLE
VCC
30µA
BOOSTCIRCUIT
I/O VL_
VL VCC
BOOSTCIRCUIT
VCCVL
I/O VCC_
NOTE 1: THE MAX14548E/MAX14548AE ARE ENABLED WHEN VL < VCC - 0.2V AND EN = VL.
100Mbps, 16-Channel LLTs
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Unidirectional vs. Bidirectional Level Translator
The devices bidirectional level translators can operate as a unidirectional device by selecting one I/O as the input and the corresponding I/O as an output. These devices provide the smallest solution (WLP package) for level translation applications.
ESD ProtectionAs with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The I/O VL_ and I/O VCC_ pins have extra protection against static electricity.
ESD Test ConditionsESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results.
Human Body ModelFigure 5a shows the Human Body Model, and Figure 5b shows the current waveform it generates when dis-charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kI resistor.
Use with External Pullup/Pulldown Resistors
Due to the architecture of the devices, it is not recom-mended to use external pullup or pulldown resistors on the bus. In certain applications, the use of external pullup or pulldown resistors is desired to have a known bus state when there is no active driver on the bus. The devices include internal pullup current sources that set the bus state when the device is enabled. In shutdown mode, the state of I/O VCC_ and I/O VL_ is high imped-ance.
Open-Drain SignalingThe devices are designed to pass open-drain as well as CMOS push-pull signals. When used with open-drain signaling, the rise time is dominated by the interaction of the internal pullup current source and the parasitic load capacitance. The devices include internal rise time accelerators to speed up transitions, eliminating any need for external pullup resistors. For applications such as I2C or 1-WireM that require an external pullup resistor, refer to the MAX13046E and MAX13047E data sheets.
Figure 5a. Human Body ESD Test Model Figure 5b. Human Body Current Waveform
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
CHARGE-CURRENT-LIMIT RESISTOR
DISCHARGERESISTANCE
STORAGECAPACITOR
Cs100pF
RC 1MΩ
RD 1500Ω
HIGH-VOLTAGE
DCSOURCE
DEVICEUNDERTEST
IP 100%90%
36.8%
tRLTIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING(NOT DRAWN TO SCALE)
Ir
10%0
0
AMPS
100Mbps, 16-Channel LLTs
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E Typical Operating Circuit
Chip InformationPROCESS: BiCMOS
Package InformationFor the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
1µF
+1.8V
+1.8VSYSTEM
CONTROLLER
+2.8VSYSTEM
PF PF
EN
DATA16
GNDGND GND
I/O VL_ I/O VCC_
EN
DATA
+2.8V
VL VCC
1µF 0.1µF
MAX14548AMAX14548AE
16
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 WLP W402B3+1 21-0437
100Mbps, 16-Channel LLTs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 17
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 4/10 Initial release —