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1
A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization
in 65nm CMOS
Yong Liu1, Byungsub Kim1,2, Timothy O. Dickson1, John F. Bulzacchelli1,
and Daniel Friedman1
IBM T.J. Watson, Yorktown Heights1
Massachusetts Institute of Technology2
ISSCC, San Francisco, Feb. 8-12 2009
10-2
2
• Introduction: silicon carrier channel
• Compact I/O with DFE-IIR equalization– Termination– Equalization– Circuit details
• Implementation and measurement
• Conclusions
Outline
3
Short-Reach Links on Silicon Carrier
• Advantage: high wiring density ultra-high chip-to-chip aggregate bandwidth
• Key I/O goal: low area and power costs
Si carrier wiring
Si substrate
Through-silicon vias
Chip 2Chip 1
BEOL Cu wirespitch: 0.5-10 μmlength: 1-50 mm I/O pitch: 10-50 μm
μC4
• Silicon carrier: silicon with BEOL used as dense packaging medium
Ref: J. Knickerbocker, JSSC 2006, p. 1718
4
Silicon Carrier Transmission LinesExample of differential wire pair in striplinestructure
• Wires are narrow and thin– Significant resistive losses for lengths >5 mm– Equalization needed for long channels
Simulated eye diagrams @5 Gb/sL=2.5 mm L=7.5 mm
L=10 mm L=20 mm
Power or Ground
Power or Ground
1.21.6
1.6
1.2
1.2
1.2
1.2
(Unit: μm)
5
Characteristics of Si Carrier Channels
Main cursor
H1H2
• Long silicon carrier channels:– Significant DC attenuation– Smoothly varying S21 curve– Long impulse response tail
20mm Si carrier channel characteristics
-6dB@DC
-17dB@5GHzH3H4H5H6
6
• Introduction: silicon carrier channel
• Compact I/O with DFE-IIR equalization– Termination– Equalization– Circuit details
• Implementation and measurement
• Conclusions
Outline
7
• Power/performance joint optimization yields– Low-Z Tx (< 50 Ω) for high drive strength– High-Z Rx (e.g., 1 KΩ) for low power dissipation
• Is the performance impact acceptable?
Tx, Rx Termination Strategy for Si Carrier Links
Tx Rx
+_
RTX
RRX
Z0, l, α, β
V+(t)V+(t-τ)
V-(t)
Si carrier channel: Z0=50~80 Ω
8
Tx Termination Strategy Analysis• Low-Z Tx (< 50 Ω) provides better
performance than 50-Ω terminated Tx
Simulated eye diagrams of Tx output
RTX<50 Ω40 mm channel 10 Gb/s
RTX=50 Ω10 mm channel 5 Gb/s
9
Rx Termination Strategy Analysis• Key issue: reflections due to mismatch
–Long links(> 7.5 mm): mitigated by lossy channels–Short links: detailed study required
Simulated Rx eye diagrams @10 Gb/s, RTX<50 Ω, RRX=1 KΩ
50 ps (0.5 UI)(worst-case)
33 ps16 psChannel Delay
7.5 mm5 mm2.5 mmChannel Length
Rx Eye
• Conclusion: minor performance impact
10
Background: Decision Feedback Equalization (DFE)
• 2-tap DFE: Set H1 and H2 tap weights to cancel the ISI of the previous two bits
DataSource
Summer Quantizer
Channel (bandwidth limited)
+
H1
H2
- -+
H2H1
11
Main cursor
~H2e-t/τ
H1H2H3 H4 H5 H6
• Minimal precursor content–Tx: no FFE
• Extended postcursor tail–Rx: high tap count DFE (ideally)
Equalization Strategy for Si Carrier Links
• Challenge: to achieve the performance of high tap-count DFE without paying area and power penalty
• Strategy: to take advantage of Si carrier channel characteristics to meet the challenge
12
Compact low-power Rx: DFE with IIR Filter
VIIR
CLK
DOUTDIN
DFE summer Latch
IIR filter
H1
VSE+- -
+
H2e-t/τ
t
g(t)
• Observation: Si carrier channel impulse response well modeled by 1 discrete tap and 1 continuous-time filter
• Solution: DFE with 1 discrete tap and 1 adjustable continuous-time IIR filter-driven tap
Main cursor
~H2e-t/τH1
H2H3 H4 H5 H6
13
Half-Rate DFE-IIR Rx Architecture
• Key features:- Slicer, DFE summing stage merged- Full-rate adjustable continuous-time IIR filter + Mux- High-speed double-regenerating latch
CLK
CLK
DO
DE
H1O
CLK
DIN
DFE summer/slicer Latch
Latch
IIR filter
DFE summer/slicer
H1E
Mux
VSUME
VSUMO
+
+
G(s)τ=RC
- -+
+- -
VIIR
14
DFE Summer/Slicer
• Summer architecture: high speed, low-power– Current integrator mitigates settling time constraint– Resettable current-comparator PMOS load (slicer)
• Transconductor configuration– Linear: input, continuous-time IIR filter feedback– Nonlinear: discrete H1 feedback, offset compensation
VIIR VIIRRTERMRTERM
DIN
VSUM
DIN
H1
VSUM
H1 VOS VOS
CLK CLK
CLK CLK
VTERM VTERM
Input Discrete Continuous Offset Comp.
15
Operation of the DFE Summer/Slicer
DINDIN
Input holdOutput regenerate
Input sampleOutput reset
RTERM
DIN DINCLK CLK
CLK CLK
VTERM VTERM
VSUM
VSUM
DSADSA DSA
DSA
VSUMVSUM
CLKCLK
Ref: T. Dickson, VLSI 2008, p. 58time
16
IIR Filter Merged with Mux
• Motivation for mux: to simplify IIR filter (full-rate channel)• Time constant controlled by RD and CD
• Amplitude controlled by RD and ID
DO DO DO
CLK CLK
DE DE DE
CLK
ICM-ID ICM+ID
RDRD
RCM
CD VIIR
VIIR
CLK
CLK
CLKDO
DE
CLK+
+
G(s)
- -+
+--
DFE-IIR Rx
17
Double-Regenerating Latch
Key features:• High speed: two-stage
data regeneration• CMOS, CML compatible
CLK CLK
OUT OUTIN IN
L1L1
L1L1
CLKCLK
ININ
Input regenerate Output hold
OUTOUT
CLK
CLKDO
DE
+
G(s)
-+
+--
DFE-IIR Rx+-
time
18
Full-Rate Transmitter
• Driver selection based on channel characteristics–Full swing for long channel–Reduced swing for short channel
DFF
DIN
DOUT
CLK
Driver
VDD
VLO
DBUF
DBUF DOUT
DBUFDOUT
DBUF
DBUF DOUT
Full-swing driver
Reduced-swing driverVDD
VLO
DBUFDOUT
DBUF
DBUF DOUT
Ref: K. Wong, JSSC 2004, p. 602
19
• Introduction: silicon carrier channel
• Compact I/O with DFE-IIR equalization– Termination– Equalization– Circuit details
• Implementation and measurement
• Conclusions
Outline
20
Compact I/O Test Site Overview• Technology:
– IBM 65 nm bulk CMOS• List of test sites:
– Rx (4): • 5 and 10 Gb/s DFE-IIR, 50 Ω terminated• 5 and 10 Gb/s 2-tap DFE, 50 Ω terminated
– Tx (2): • 10 Gb/s full swing• 10 Gb/s reduced swing
– Tx-channel-Rx (12): • Channel realized on-chip, emulates Si carrier
channel– Emulated channel measurement macro
21
Si Carrier-like Channels: Lossy PCB Traces
Impulse responsesTransfer functions
PCB Traces
Note: setup adds ~2 dB additional loss
-12.7 dB-16.9 dB-21.0 dB
Time (ns)20 4 6 8 10
-30
-20
-10
0
S21
(dB
) 0.81.0
0.60.40.2
0A
mpl
itude
30” Trace40” Trace50” Trace
30” Trace40” Trace50” Trace
0 0.4 0.8 1.6 2.01.2Frequency (GHz)
22
Stand-Alone DFE-IIR Rx Performance: PCB Traces
• Power dissipation: 7 mW from 1.0 V power supplyBathtub curves (PRBS7) @ 10 Gb/s
57%
45%
71%
23
16” Tyco Backplane Channel
Note: setup adds ~2 dB additional loss
Impulse responseTransfer function
Backplane Channel
-25 dB
Time (ns)0 0.2 0.4 0.80.620 4 6 8 10
Frequency (GHz)
-40
-20
-100
S21
(dB
) 0.75
1.0
0.5
0.25
0A
mpl
itude
-30
24• Power dissipation: 7 mW from 1.0 V power supply
Bathtub curve (PRBS7) @ 10 Gb/s
28%
Stand-Alone DFE-IIR Rx Performance:16” Tyco Channel
25
Stand-Alone Test Sites Results Summary
Pattern 2-tap DFE[7mW from 1V]
Horizontal eye opening (BER<1e-9) @ 10Gb/s
Channel DFE-IIR[7mW from 1V]
Closed eye28%PRBS716” Tyco
Closed eye45%PRBS750” trace
Closed eye41%PRBS31
28%57%PRBS740” trace
24%57%PRBS31
47%71%PRBS730” trace
• Tx: full/reduced swing designs fully functional 10.8 Gb/s• Rx: DFE-IIR fully functional (open eye: 13 Gb/s) with
64 mVppd input sensitivity at 10 Gb/s
Carrier likePCB channels
Backplanechannel
26
Tx–Emulated Channel–Rx Test Site
Emulatedsiliconcarrier
channels
25 mm x 5
17 mm40 mm x 2
Tx Rx75 μm
75 μm
115 μm
150 μm
12 Tx 12 Rx10 mm x 32 mm
5 mm
2 mm
27
Emulated Channel Characterization
Line13.2mm
Open Short
Line11.9mm
-29dB
-33dB(23dB rolloff)
Extrapolate
Channel macro
• Goals:– Characterize on-chip channel characteristics– Compare to actual carrier channel data to ensure
results are relevant to target application
Emulation in CMOS backendSi carrier channel (measured)
25-mm lines
40-mm lines
(22dB rolloff)
28
Tx- Emulated Channel-Rx Test Setup
Data Generator
PC
Clock Source
Full-rateData & Clk
Tx Rx
Emulated channels
Divider
1/2
Error Detectors
Test Site Chip
Half-rateData & Clk
Serial Data
Interface
Delay Tuning
29
Tx–Emulated Channel–Rx Test Results
Operation demonstrated across wide range of channels
TX
Channel
ESD
RX
Fullswing
Fullswing
Fullswing
Reducedswing
Fullswing
Fullswing
Fullswing
Reducedswing
Reducedswing
Reducedswing
40 mm 25 mm 25 mm 25 mm 25 mm 25 mm 17 mm 10 mm 10 mm 10 mm 2 mm
No No Yes No No Yes Yes No Yes No Yes
Fullswing
DFE-IIR DFE-IIR DFE-IIR 2-tap DFE DFE-IIR DFE-IIR DFE-IIR 2-tap
DFE2-tap DFE
2-tap DFE
2-tap DFE
8.99.5
9.0
6.7 6.9 6.8
10 10 9.7 9.9 10.8
1.9 1.92.3 2.5
1.5 1.5 1.8 1.5 1.6 1.1 1.3
Max data rate (Gb/s)(15% eye opening@ BER=10-9)
Power efficiency(mW/Gbps)
longestchannel
bestpower
efficiency
30
Conclusions
• Silicon carrier channel characteristics are well suited to– Low-Z Tx, high-Z Rx terminations– DFE-IIR based equalization approach
• DFE-IIR Rx performance demonstrated over range of channels– Smoothly varying PCB channels (>20 dB loss)– Legacy backplane: 16” Tyco channel (27 dB loss)– Emulated carrier channels, e.g., 40 mm (22 dB loss)
@ 8.9 Gb/s, 1.9 mW/Gbps
31
Acknowledgements
• IBM Yorktown Research team:• Chirag Patel, Michael Beakes, Donald W. Beisser,
Keith Jenkins, Ben Parker, Alexander Rylyakov, Daniel M. Kuchta, Arun S. Natarajan, XiaoxiongGu, Dong G. Kam, Zeynep Toprak Deniz, SudhirGowda, and Mehmet Soyuer
• We gratefully acknowledge partial support of this work through MPO contract #H98230-07-C-0409