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Workshop Topics - OutlineWorkshop 1 - IntroductionWorkshop 2 - module instantiationWorkshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types AWorkshop 6 - Data types B Workshop 7 - OperatorsWorkshop 8 - Signed arithmetic Workshop 9 - Behavioral modelingWorkshop 10 - Data flow modelingWorkshop 11 - Tasks and FunctionsWorkshop 12 - Advanced Modeling TechniquesWorkshop 13 - Coding Styles and Test Benches

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Workshop 7 - Operators

Expressions and OperandsOperators TypesBus OperatorsArithmetic OperatorsBitwise OperatorsReduction OperatorsLogical OperatorsRelational OperatorsConditional OperatorOperators Precedence

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Expressions and OperandsExpressions are constructs that combine operators and

operands to produce a result.Operands can be any one of the data types defined in the

previous lecture: integers real numbers nets registers times bit-select (one bit of vector net or vector register) part select (selected bits of vector net or vector register) memories function calls (discussed later)

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OperatorsOperators are of three types:

Unary Binary Ternary

Unary operators precede the operandBinary operators appear between two operandsTernary operators have two separate operators that

separate three operands a = ~ b ; // ~ is a unary operator. b is the operand

a = b && c ; // && is the binary operator. a and b are operands

a = b ? c : d ; // ?: is a ternary operator. b, c and d are operands

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Bus Operators

A = 8'b10001011

Operator Example

[ ]

{ }

{{ }}

<<

>>>

>>

Description

Bit/Part Select

Concatenation

Replication

Shift left logical

Shift right arithmetic

Shift right logical

A[0] = 1'b1; A[5:2] = 4'b0010 ;

{A[5:2],A[7:6],2'b01} = 8'b00101001

{3{A[7:6]}} = 6'b101010

A<<2 = 8'b00101100

A>>3 = 8‘b00010001

A>>>3 = 8‘b11110001

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Arithmetic Operators

A = 8'b10001011 = 139 B = 8’b00001100 = 12

Operator Example

+

-

*

/

%

Description

Addition

Subtraction

Multiplication

Division

Modulus

A + 12 = 151 = 8‘b10010111

A – 10 = 129 = 8‘b10000001

A * 3 = 417 = 9‘b110100001

A / 2 = 69 = 7'b1000101

A % 5 = 4 = 3'b100

** Power (exponent) B ** 2 = 144 = 8'b10010000

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Bitwise Operators

A = 8'b10001011

Operator Example

~

&

|

^

~^

Description

Inverse / NOT

AND

OR

XOR

XNOR

~A = 8'b01110100

A[2] & A[1] = 1'b0

A[2] | A[1] = 1'b1

A[2] ^ A[1] = 1'b1

A[2] ~^ A[1] = 1'b0

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Reduction Operators

A = 8'b10001011

Operator Example

&

~&

|

~|

^

Description

AND

NAND

OR

NOR

XOR

&A = A[0] & A[1] & … A[7] = 1'b0

~&A = ~(A[0] & A[1] & … A[7]) = 1'b1

|A = A[0] | A[1] | … A[7] = 1'b1

~|A = ~(A[0] | A[1] | … A[7]) = 1'b0

^A = A[0] ^ A[1] ^ … A[7] = 1'b0

~^ XNOR ~^A = ~(A[0] ^ A[1] ^ … A[7]) = 1'b1

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Logical Operators

A = 8'b10001011 Operator Example

!

&&

||

==

!=

Description

NOT

AND

OR

EQUAL

NOT EQUAL

!A[1] = FALSE, !A[2] = TRUE

A[0] && A[1] = TRUE

A[0] || A[2] = TRUE

A[3:0] == 4'b1011 = TRUE

A[3:0] != 4'b1011 = FALSE

<,<=,>,>= COMPARE A[3:0] < 13 = TRUE

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Relational Operators>, >=, <, <= : Determine relative value.

Registers and nets are treated as unsigned. Real and Integer operands, may be signed. If any bit is unknown, the result will be unknown. Result is one bit value: 0, 1 or X

==, != : Logical equality, inequality.Registers and nets are treated as unsigned. Real and Integer operands, may be signed. If any bit is unknown (or high-impedance), the result will be unknown. 1-bit result 0, 1 or X

===, !== : case equality, inequality.The bitwise comparison includes X and Z values. All bitsmust match for equality. The result is either True or False.4 ‘b 110Z == 4 ‘b110Z => FALSE

4 ‘b 110Z === 4 ‘b 110Z => TRUE

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Conditional OperatorThe conditional operator (?:) can be used in place of the

if statement when one of two values is to be selected for assignment.

The general form of the conditional operator is: :: = <cond_expression> ? <true_expr> : <false_expr> ;If the first expression is TRUE, then the value of the

operator is the second expression. Otherwise the value is the third expression.

May be a part of a procedural or continuous statement. Conditional operator can be used both in behavioral and

gate level structural modeling.Example: 2-to-1 MUX Y = (sel)? A : B ; B

Y

sel

0

1A

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Operators Precedence

Operators Operators Symbols

UnaryMultiply, Divide, ModulusAdd, Subtract

Shift

Equality Relational

+ - ! ~* / %+ -<< >> >>>

< <= > >=

== != === !==

Reduction Logical Conditional

&, ~&, ^, ^~, |, ~| &&?:

Highest Precedence

Lowest Precedence

If no parentheses are used to separate operands then Verilog uses the following rules of precedence: (good practice: use parentheses)