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Timing-Driven Synthesis for Timing-Driven Synthesis for

Fast Barrel ShiftersFast Barrel Shifters

Sabyasachi DasSabyasachi DasUniversity of Colorado, BoulderUniversity of Colorado, Boulder

Sunil P. KhatriSunil P. KhatriTexas A&M UniversityTexas A&M University

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What is a Shifter?What is a Shifter?

IC block that performs shifting of data IC block that performs shifting of data signals signals

Well-known logic architecturesWell-known logic architectures

Computationally-intensiveComputationally-intensive Occupies significant amount of areaOccupies significant amount of area

Wide usage in DSP, Graphics, Wide usage in DSP, Graphics, MicroprocessorsMicroprocessors

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Introduction to Barrel Introduction to Barrel ShifterShifter

Widely used Shifter architecture Widely used Shifter architecture

Exhibits good timing characteristicExhibits good timing characteristic

Area-efficient as wellArea-efficient as well

Inherent regularity in physical Inherent regularity in physical structurestructure

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Structure of Barrel Structure of Barrel ShifterShifter

Width of input and output data signals = n bitsWidth of input and output data signals = n bits

Width of input shift signal = logWidth of input shift signal = log22n bitsn bits

Shifter consists of logShifter consists of log22n stagesn stages

Each bit of the shift signal controls one stageEach bit of the shift signal controls one stage

Each stage handles single shift of 0 or 2Each stage handles single shift of 0 or 2ii bits bits

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Example of a Barrel Shifter Example of a Barrel Shifter (2-stage)(2-stage)

S0 = 1’b1

s0

x2 x1

s0

x3 x2

s0

x0 1’b0

s0

x1 x0

s1s1

s1s1

1’b0 1’b0

z0z3z2

z1

S1 = 1’b0

1’b0x0x1

x2

x2 x1x0 1’b0

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Proposed Dual-Merged Proposed Dual-Merged StageStage

Merge stages i and jMerge stages i and j

4 bit input data signal4 bit input data signal

2 bit shift signal2 bit shift signal

i and j do not need to i and j do not need to be two consecutive be two consecutive bits of the shift signalbits of the shift signal

xa xb xc xd

sisj

zij

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Proposed Dual-Merged Proposed Dual-Merged StageStage

For the qFor the qthth BitSlice (Column) of a left shifter BitSlice (Column) of a left shifter xxaa = x = xq q

xxbb = x = x(q-(q-22ii) )

xxcc = x = x(q-(q-22jj) )

xxdd = x = x(q-(q-22ii--22jj) )

For the qFor the qthth BitSlice (Column) of a right shifter BitSlice (Column) of a right shifter xxaa = x = xq q

xxbb = x = x(q+(q+22ii) )

xxcc = x = x(q+(q+22jj) )

xxcc = x = x(q+(q+22ii++22jj))

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Example of a 2-Stage Shifter Example of a 2-Stage Shifter Using Dual-Merged StagesUsing Dual-Merged Stages

s0

x3 x2 x1 x0

s1

z3

s0 s1

z2

s0 s1

z1

s0 s1

z0

x2 x1 x0 0 x1 x0 0 0 x0 0 0 0

S1S0 = 2’b01

x1x2 x0 1’b0

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Proposed Triple-Merged Proposed Triple-Merged StageStage

Merge stages i, j Merge stages i, j and kand k 8 bit input data 8 bit input data

signalsignal 3 bit shift signal3 bit shift signal

i, j and k do not i, j and k do not need to be three need to be three consecutive bits consecutive bits of the shift signalof the shift signal

xe xf xg xh

sisj

zijk

sk

xa xb xc xd

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Triple-Merged StagesTriple-Merged Stages

For the qFor the qthth BitSlice (Column) of a left shifter BitSlice (Column) of a left shifter xxaa = x = xq q

xxbb = x = x(q-(q-22ii) )

xxcc = x = x(q-(q-22jj) )

xxdd = x = x(q-(q-22kk) )

xxee = x = x(q-(q-22ii--22jj) )

xxff = x = x(q-(q-22ii--22kk))

xxgg = x = x(q-(q-22jj--22kk))

xxhh = x = x(q-(q-22ii--22jj--22kk))

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Identification of Identification of Mergeable StagesMergeable Stages

Timing-driven algorithmTiming-driven algorithm

Uses arrival-time of the shift signalsUses arrival-time of the shift signals

Uses the timing characteristic of the Uses the timing characteristic of the technology library cellstechnology library cells

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Algorithm to Find Algorithm to Find Mergeable StagesMergeable Stages

Sort shift signals by arrival time (SSort shift signals by arrival time (Sii, S, Sjj, S, Skk are are earliest)earliest)

Analyze dual-merged stage, triple-merged stage Analyze dual-merged stage, triple-merged stage and unmerged stage to decide whetherand unmerged stage to decide whether To create a triple-merged stage by merging stages i, j To create a triple-merged stage by merging stages i, j

and k and k To create a dual-merged stage by merging stages i and jTo create a dual-merged stage by merging stages i and j To create an unmerged stage for the stage iTo create an unmerged stage for the stage i

Continue analysis with the next three stages Continue analysis with the next three stages corresponding to the 3 earliest arriving shift bits.corresponding to the 3 earliest arriving shift bits.

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Analysis of an Unmerged Analysis of an Unmerged StageStage

si

xa xb

sj

skArr_T(sk)

xc

xd Arr_T(sj)

Arr_T(si)

Tsingle

Compute the impact of an unmerged stage (i)Compute the impact of an unmerged stage (i) TTsinglesingle = Arr_T (si) + Del = Arr_T (si) + Del11

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Analysis of Two Analysis of Two Unmerged StagesUnmerged Stages

si

xa xb

sj

skArr_T(sk)

xc

xd Arr_T(sj)

Arr_T(si)

Tsingle2

Compute the impact of 2 cascaded unmerged Compute the impact of 2 cascaded unmerged stagesstages Tsingle2 = Max (Tsingle, Arr_T (sArr_T (sjj))) + Del1

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Analysis of Three Analysis of Three Unmerged StagesUnmerged Stages

si

xa xb

sj

skArr_T(sk)

xc

xd Arr_T(sj)

Arr_T(si)

Tsingle3

Compute the impact of 3 cascaded unmerged Compute the impact of 3 cascaded unmerged stagesstages Tsingle3 = Max (Tsingle2, Arr_T (sArr_T (skk))) + Del1

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Analysis of a Dual-Analysis of a Dual-merged Stagemerged Stage

Arr_T(si)

Tdual

Compute the impact of a dual-merged stage (i, Compute the impact of a dual-merged stage (i, j)j) TTdual dual = Arr_T (s= Arr_T (sjj) + Del) + Del22

xa xb xc xd

sisj

zij

Arr_T(sj)

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Analysis of a Triple-Analysis of a Triple-merged Stagemerged Stage

Arr_T(si)

Ttriple

Compute the impact of a triple-merged stage Compute the impact of a triple-merged stage (i, j, k)(i, j, k) TTtriple triple = Arr_T (s= Arr_T (skk) + Del) + Del33

Arr_T(sj)

xe xf xg xh

sisj

zijk

sk

xa xb xc xd

Arr_T(sk)

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Selection of Mergeable Selection of Mergeable StagesStages

If (TIf (Ttripletriple<<Tsingle3) and (T) and (Ttripletriple<(<(Tdual + + Del1/2))/2)) Implement triple-merged stage (for stages i, j Implement triple-merged stage (for stages i, j

and k)and k)

Else if (TElse if (Tdualdual<<Tsingle2) ) Implement dual-merged stage (for stages i Implement dual-merged stage (for stages i

and j)and j)

ElseElse Implement single unmerged stage for stage iImplement single unmerged stage for stage i

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ResultsResults

On an average, 10.19% faster than the resultof the commercial Datapath Synthesis tool

0

500

1000

1500

2000

2500

3000

Shifter-16 Shifter-32 Shifter-64 Shifter-128

Type of Shifter Block

Wo

rst

D

ela

y

Delay of the Traditional Barrel Shifter Delay of Our Proposed Barrel Shifter

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SummarySummary

Merge 2 stages to form Dual-Merged stageMerge 2 stages to form Dual-Merged stage

Merge 3 stages to form Triple-Merged stageMerge 3 stages to form Triple-Merged stage

Timing-driven algorithm to identify mergeable Timing-driven algorithm to identify mergeable stagesstages

Reduces the number of stages upto one-third Reduces the number of stages upto one-third (33.33%)(33.33%)

On an average, 10.19% fasterOn an average, 10.19% faster

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Thank youThank you