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1
Power Management for High-speed Digital Systems
Tao Zhao
Electrical and Computing Engineering
University of Idaho
2
Motivation Smaller CMOS process brings faster
switching time and lower VDD
Power efficiency: static power consumption goes larger
Power integrity: voltage noise margin becomes smaller
3
How high is high-speed?
Options: A. >1KHz B. >1MHz C. >1GHz
It is when the passive components come in to play and even dominate the behavior of the circuits, the speed is high-speed
High-speed digital system study is a study of the behavior of passive components
4
Where are the passive circuits?
dIV L
dt
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Reduce VDD and increase VSS
The problem becomes more serious when VDD goes lower
Low impedance path between VDD and ground All frequencies of interest have to be covered
Where are the passive circuits?
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How high do we have to care?
Clock frequencies
0.5
RISET
Signal Rise and Fall Time
FKNEE=
7
How high do we have to care?
FKNEE=0.5
RISET
=500MHz
TRISE=1ns
FCLOCK=25MHz
32-bit reconfigurable data processor, always a slave Maximize throughput, minimize control Multiple chips can be tiled to extend the size of the data
path Current revision: 250nm process, 250K gates, runs at
25MHz, radiation-hardened 16 pairs of power and ground pins
Field Programmable Processing Array
Serves as memory for the FPPA Include memory address control and 1MB RAM Like the FPPA, multiple RMMs can be tiled too RMM has only been simulated in software, but
not been fabricated Assume the RMM has the same DC
characteristics as the FPPA
Reconfigurable Memory Module
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The Reconfigurable Platform
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Power Domain
Power Budget
DC characteristic Target impedance
argt et
VoltageSupply MaximumNoiseZ
MaximumCurrent
2.5 5%
0.2
V
A
0.625
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Power Delivery Path
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Voltage Regulator
Linear vs. Switching
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low efficiency low noise level cheap
high efficiency high noise level expensive
Voltage Regulator
Linear Voltage Regulator
Switching Voltage Regulator
Supply desired voltage level Supply enough current Radiation hardened
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Wiring Impedance
• Wiring Resistance is negligible• V=L*di/dt
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Decoupling Capacitor (Decap)
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Bulk Capacitor• ESL• Self-resonant frequency
1
2SRF
ESL C
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Parallel Ceramic Capacitors
• Self-resonant at higher frequency• parallelism
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Ceramic Capacitor Selection
C (μF) Fsr (MHz) Fsw (MHz) Zsw (mΩ)1 5 6.3 1020.47 7.3 12.4 1130.1 15.9 19.9 1110.047 23.2 39.2 1890.01 50 63 1740.0047 73.4 124 21680.001 159.1 N/A N/A
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Ceramic Capacitor Array
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Ceramic Capacitor Array
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Decoupling Capacitor Network
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Dynamic Power Management Subsystems can be powered up and down in runtime High-side load switch
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Power-up Challenge
Free from big current spike, monotonic voltage ramp-up
Don’t upset the rest of the system Decoupling capacitor network adds load
capacitance: internal capacitance (nF); decap (μF)
Inrush current: I=C*dV/dt I=C*dv/dt=5 μF*2.5V/1 μs=12.5A
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Soft Start-up
Small dV/dt rate substantially reduces inrush current
Soft start: longer time, less current The rise time of the gate voltage determines the
turn-on time of the PMOS
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Slew-rate Controllable High-side Load Switch
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Reduce Inrush Current
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Sequencing and Voltage Supervisor
Commercial products -- ADM1066 Programmable Sequencer
10 channels for sequencing and 12 channels for supervising
Contain a state machine to control the sequencing and supervising
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Conclusion
High-speed digital design focuses on the behaviors of passive circuits
Digital system design trends: lower VDD requires better power integrity and power efficiency
31
Conclusion
Design flow: Power budget Choose the right voltage regulator Design decoupling capacitor network to filter
voltage noise Use soft-start and sequencing start-up to
prevent big inrush current Voltage supervisor
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Future Work
Measurement: accurate numbers Board level interconnection: LVDS Lower voltage: Better power integrity
Dr. Gregory Donohoe Dr. Kenneth Hass Dr. Robert Rinker All the FPPA team members
Acknowledgement
34