1

Hierarchical, physical-aware, built-in self-repair of embedded memories

V.R. Devanathan, Harsharaj Ellur, Mohd. Imran, Shivani Bathla

Texas Instruments India Pvt. Ltd.

{vrd, harsharaj.ellur, m-beg, shivani}@ti.com

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2

Area overhead

0

100

200

300

400

500

600

A[0.5Mb]

B[0.8 Mb]

C[6.4 Mb]

D[8.8 Mb]

E[10.0 Mb]

F[45.8 Mb]

IP Cores

# g

ate

s (

K)

BIST DP

BIRA DP

FuseROM

Motivation

Need area efficient memory test/repair flow over native

EDA solution, with support for incremental repair■ Total test and repair area overhead as high as 1M gate!

3

Optimizing BIST datapath[1]

Automated, physical-aware grouping to ease congestion

Timing & interconnect-aware pipelining to ease timing closure

[1] V. R. Devanathan, et. al., “Novel approaches for effective and optimized memory test flow in nanoscale technologies” , VTS 2012

Grp1

Grp2

Grp3Grp4

Grp5

LEGEND : Level 0 TIA pipelines

: Level 1 TIA pipelines

: Level 2 TIA pipelines

Pipelines assigned on each data-pathbranch using TIA heuristics

LEGEND : Level 0 Group

: Level 1 Group

: Level 2 Group

Grp1

Grp2

Grp3Grp4

Grp5

Physical-aware grouping of clusters

4

Optimizing BIRA datapath

Physical-aware sharing of BIRA across multiple memories■ Group temporally separated memories, with similar repair code

Timing and interconnect-aware BIRA data-path pipelining

BIRA BIRA

BIRABIRA

Grp1

Grp2

Grp3Grp4

Grp5

BIRA architectureoverview

BIRA

Grp1

Grp2

Grp3Grp4

Grp5

BIRA data-path grouping overview

BIRA BIRA

BIRABIRA

Grp1Grp2

Grp3 Grp4

Grp5BIRA execution on Grp2

BIRA BIRA

BIRABIRA

Grp1

Grp2

Grp3 Grp4

Grp5BIRA execution on Grp3

BIRA

BIRABIRA

Grp1

Grp2

Grp3 Grp4

Grp5BIRA execution on Grp4

BIRA

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Proposed self-repair execution flow

EFUSE

BISoR + BIRA

M1FDOFDI

M2FDOFDI

M6

FDOFDI

M3FDOFDI

M4

FDOFDI

M5

FDOFDI

FuseROMPBIST

MemGrp1

MemGrp2

Soft-repair group 1Soft-repair group 2Hard-repair on SoCTest group 1Test group 2

6

Optimizing Fuse ROM storage

REPAIRING MEM0, MEM2 & MEM5INCREMENTAL REPAIR ON MEM1 & MEM3

Dynamic re-configuration of memory fuse chain■ Store only repaired memory data in FuseROM

Support for incremental repair with intelligent bypass wrappers

7

Robust repair verification flow

BIRA & BISoR shared across different memories, with different configurations. ■ Need fool-proof verification on each memory.

Mem0

FDO

Q

FDIBIRA

Repair code

Mem_Q

Per-instance unique fail injection

TCL based fuse register

comparator

Expected fuse register value

Soft unload

PASS

FAIL

Soft repair

Mem0

FDO

Q

FDI

BISoR VerificationComplete

Check BISoR integration /

flow parameters

Mem0

TCL based fault injection

PBIST

Q

FDI

FDO

Run BIST with self-repair

Run BIST with self-repair

Run BIST post-self-repair

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PD flylines for level-0 + level-1datapath routes for a SoC core,

with the proposed flow

PD flylines for level-0 + level-1datapath routes for a SoC core,

without physical-aware flow

Results: BIST and Repair data-path area

Reduced congestion with proposed BIST/BIRA data-path grouping

Significant (~6X) area reduction over native EDA solution

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Results: FuseROM area

Significant area reduction without (and with) incremental repair■ Compaction-based native EDA solution: 2.3X (and ~44%)■ Proposed dynamic re-configuration: 6.6X (and 4.5X)

Compaction (native EDA solution) may be used over the

proposed technique for further area reductionFuseROM area with incremental repair

0

100

200

300

400

500

600

A B C D E FCore

#g

ate

s (

K)

Conventional unoptimized

Conventional compacted

Proposed

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Conclusion

A novel self-repair flow is presented, that provides■ ~6X reduction in data-path area, over native EDA flow ■ ~2.5X reduction in FuseROM area, over native EDA flow■ Automated, physical-design friendly generation of

structured BISR data-path■ Incremental repair support

Proposed flow is vendor-agnostic and pluggable into

vendor EDA BISR solution

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Thank You!

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Built-In Soft-Repair (BISoR) controller

Soft-repair triggered by PBIST after test of each group. ■ Each BIRA/BISoR is shared across ‘N’ memory groups.

Mem0

FDI FDI

FCLK

QMem0

FDI FDI

FCLK

QMem0

FDO FDI

FCLK

Q

Repair code

CG

. . .0

Fuse_length per mem_ID

CG

Mem_ID

Trigger

Fuse_clkBira_fclk

fuse clock leaker

CGCGBISoR

fclk

Mem_Q

Mem_ID

Mem_fclk[N-1:0]

Mem_ID

Repair code

BIRAFail encode

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Built-in Hard-repair controller

EFUSE controller enhanced for hard-repair■ Shift out soft-repaired memory fuse chain, slice data wrt FuseROM

data-width (W), and automatically blow/write data into FuseROM

M0 M1 M2 MM-2 MM-1…

Memory Fuse Register Chainfdi fdo

EFUSE

W

…

W

Control / reserved bits

C

R

Fuse ROM

Fuse auto-unloadFuse auto-load

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Support for incremental repair: BISoR

Minor enhancements to BIRA and BISoR■ BIRA: Merging of old repair and new repair code■ BISoR: Increased clock-leaker pulses and additional trigger

Merged repair code Init repair code

Fail encode

MergeBIRA

Mem0

FDI FDI

FCLK

QMem0

FDI FDI

FCLK

QMem0

FDO FDI

FCLK

Q

CG

. . .0

(2*Fuse_length+1) per mem_ID

CG

Mem_ID

Trigger

Fuse_clkBira_fclk

fuse clock leaker

CGCGBISoR

fclk

Mem_QMem_ID

Mem_fclk[N-1:0]

Mem_ID

Repair code

Merge_Trigger

Delay (Fuse_length per mem_ID cycles)

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Support for incremental repair: FuseROM

Bypass wrapper supporting incremental repair

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Results: BIST and Repair data-path area

Negligible (~1%) impact to test time with proposed self-

repair flow

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Results: FuseROM area

Significant area reduction without (and with) incremental repair■ Compaction-based native EDA solution: 2.3X (and ~44%)■ Proposed dynamic re-configuration: 6.6X (and 4.5X)

Compaction (native EDA solution) may be used over the

proposed technique for further area reduction