ECE 545 – Introduction to VHDL 1

Algorithmic State Machines

Sorting Example

ECE 656Lecture 8

ECE 545 – Introduction to VHDL 2

Sources & Required Reading

• Stephen Brown and Zvonko Vranesic,Fundamentals of Digital Logic with VHDL Design

Chapter 8.10Algorithmic State Machine (ASM) Charts

Chapter 10.2.6Sort Operation

ECE 545 – Introduction to VHDL 3

Algorithmic State Machine (ASM)Charts

ECE 545 – Introduction to VHDL 4

Algorithmic State Machine

Algorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of

inputs and outputs compared to FSMs expressed using state diagrams and state tables.

ECE 545 – Introduction to VHDL 5

Elements used in ASM charts (1)

Output signalsor actions

(Moore type)

State name

Condition expression

0 (False) 1 (True)

Conditional outputs or actions (Mealy type)

(a) State box (b) Decision box

(c) Conditional output box

ECE 545 – Introduction to VHDL 6

Elements used in ASM charts (2)

• State box – represents a state. Equivalent to a node in a state diagram or a row in a state table.Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place.

ECE 545 – Introduction to VHDL 7

Elements used in ASM charts (3)

• Decision box – indicates that a given condition is to be tested and the exit path is to be chosen accordinglyThe condition expression consists of one or more inputs to the FSM.

• Conditional output box – denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box.

ECE 545 – Introduction to VHDL 8

Moore FSM – Example 1: State diagram

C z 1 =

Reset

B z 0 = A z 0 = w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

ECE 545 – Introduction to VHDL 9

w

w

w 0 1

0

1

0

1

A

B

C

z

Reset

w

w

w 0 1

0

1

0

1

A

B

C

z

Reset

ASM Chart for Moore FSM – Example 1

ECE 545 – Introduction to VHDL 10

A

w 0 = z 0 =

w 1 = z 1 = B w 0 = z 0 =

Reset w 1 = z 0 =

Mealy FSM – Example 2: State diagram

ECE 545 – Introduction to VHDL 11

ASM Chart for Mealy FSM – Example 2

w

w 0 1

0

1

A

B

Reset

z

ECE 545 – Introduction to VHDL 12

Control Unit Example: Arbiter (1)

Arbiter

reset

r1

r2

r3

g1

g2

g3

clock

ECE 545 – Introduction to VHDL 13

Idle

000

1xx

Reset

gnt1 g 1 1 =

x1x

gnt2 g 2 1 =

xx1

gnt3 g 3 1 =

0xx 1xx

01x x0x

001 xx0

Control Unit Example: Arbiter (2)

ECE 545 – Introduction to VHDL 14

Control Unit Example: Arbiter (3)

r 1 r 2

r 1 r 2 r 3

Idle

Reset

gnt1 g 1 1 =

gnt2 g 2 1 =

gnt3 g 3 1 =

r 1 r 1

r 1

r 2

r 3

r 2

r 3

r 1 r 2 r 3

r 1 r 2

r 1 r 2 r 3

Idle

Reset

gnt1 g 1 1 =

gnt2 g 2 1 =

gnt3 g 3 1 =

r 1 r 1

r 1

r 2

r 3

r 2

r 3

r 1 r 2 r 3

ECE 545 – Introduction to VHDL 15

ASM Chart for Control Unit - Example 3

r 1

r 3 0 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

r 1

r 3 0 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

ECE 545 – Introduction to VHDL 16

Digital System Designwith VHDL

ECE 545 – Introduction to VHDL 17

Structure of a Typical Digital System

Execution Unit

(Datapath)

Control Unit

(Control)

Data Inputs

Data Outputs

Control Inputs

Control Outputs

Control Signals

ECE 545 – Introduction to VHDL 18

Hardware Design with RTL VHDL

Pseudocode

Execution Unit Control Unit

Blockdiagram

Blockdiagram

ASM

VHDL code VHDL code VHDL code

Interface

ECE 545 – Introduction to VHDL 19

Sorting

ECE 545 – Introduction to VHDL 20

Sort

Clock

Resetn

DataInN

DataOutN

Sorting - Required Interface

DoneRAddL

WrInit

S(0=initialization 1=computations)

Rd

ECE 545 – Introduction to VHDL 21

Simulation results for the sort operation (1)Loading the registers and starting sorting

ECE 545 – Introduction to VHDL 22

Simulation results for the sort operation (2)Completing sorting and reading out registers

ECE 545 – Introduction to VHDL 23

Sorting - Example

Beforesorting

During Sorting Aftersorting

address

0123

3 3 2 2 1 1 1 12 2 3 3 3 3 2 24 4 4 4 4 4 4 31 1 1 1 2 2 3 4

i=0 i=0 i=0 i=1 i=1 i=2j=1 j=2 j=3 j=2 j=3 j=3

Ri Rj

Legend: position of memory indexed by i

position of memory indexed by j

ECE 545 – Introduction to VHDL 24

Pseudocode for the sort operation

for i = 0 to k 2 doA = R i ; for j = i + 1 to k 1 do

B = R j ; if B < A then

R i = B ; R j = A ; A = R i ;

end if ; end for;

end for;

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