1 CS Bus Hub Arch Overview

7/28/2019 1 CS Bus Hub Arch Overview

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PC Chipset: Bus Architecture

Intel Hub

Architecture

OverviewChapter 1

Copyright 1996-2003 Intel Corp.


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PC Chipset: Bus Architecture CH-1 Slide-2

IntelHub Architecture

OBJECTIVES: At the end of this section, the

student will be able to do the following:Explain Intel Hub Architecture block diagram

Identify Intel Hub Link Bus attributes

Explain the MCH, GMCH and ICH block diagramsExplain the FWH block diagram

Describe the CNR interface

IATT Web Site:http://iatt.intel.com
http://iatt.intel.com/http://iatt.intel.com/http://smted.intel.com/smtt/


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The Chipset

consists of the

North B r idge,

South Br idgeand

Firmware Hub

M-1

ProcessorHost Bus (PSB)

100/133/200MHz

64-bit

HubLink Bus

PCI Bus

33 MHz 32-bit

AGP Bus

System

Memory

Audio

USB

LAN

IDE

Keybrd

Mouse

Floppy

SerialParallel

Clock

Gen

Host Clock

PCI Clock

USB Clock

Hublink Clock

LPC Bus

SM Bus

CNR

SIO

SouthBridge(ICH)

NorthBridge(MCH)

FWH


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IntelPC Chipsets

Include North Bridge, South Bridge and Firmware Hub

Various chipsets available from Intel to meet specificperformance requirements

Value PC (810, 815)

Pentium III or Celeron Processor

SDRAM

Integrated Graphics controller (Direct AGP)

Mainstream & Performance PCs (845, 850)

Pentium 4 ProcessorSDRAM, DDR or RAMbus

Support for AGP, DVO or Direct AGP

Support for Hyper-Threading Technology (later 845s)


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Chipset Components

The Northbridge may be either:

Memory Control ler Hub(MCH)Interfaces between the CPU and the rest of the system

Memory

AGP Bus

Hublink Bus

Graphicsand Memory Controller Hub (GMCH)

Includes integrated graphics accelerator

Supports either: (depends on version)

Direct AGP - fully integrated graphics engine - noexternal AGP slot - used for Value PC

orAGP 2.0 (with AGP slot)

Support for analog video, Digital Video Out (DVO) and DisplayData Channel (DDC)


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Which device supports"Direct AGP"?

1: MCH

2: ICH

3: GMCH

4: FWH

3: GMCH

M-1


7/24PC Chipset: Bus Architecture CH-1 Slide-7

Chipset Components

The South Bridge orI/O Control ler Hub(ICH)

Interfaces to I/O devicesPCI Bus

IDE

USB

LPC bus to Firmware Hub and Super I/O (Legacy I/O)

The Firmware Hub (FWH)

Stores BIOS code/data in 512KB or 1MB flash memory

Random number generator Can be reprogrammed in place



Proprietary point-to-point interface between MCH and

ICH Expandable to multiple Hublink bus structure in some

chipsets

Eight bit data bus, two strobe signals, 3 special signals

66.6MHz clock signal derived from AGP clock

May also be 16 bit data and/or 100MHz clock

Data can be transferred at 4 bytes per clock cycle

4 bytes x 66.6MHz clock = 266MB/sec

Hublink design and operation is Intel proprietary



Each contain PCI devices which are designated with a

one byte ID--the MCH contains 2 devices; GMCH has 3. Device 0: Host to Hub Bridge- Resides on PCI bus 0

Connects Host bus to PCI bus 0 interfaces with system

memory controller

Device 1: PCI to AGP Bridge- Resides on PCI bus 0Connects to AGP bus to extend outside the MCH

AGP bus may be designated as BUS 2

When card is plugged into AGP slot it will be Bus 2:Device 0

Device 2: Graphics Accelerator (GMCH only) on PCI Bus 0

Analog video out (VGA)

Digital video out

Display Data Channel (DDC for plug and play monitor)



MCH PCI Devices

Host-Hub Bridge

B0:D0:F0

Hub

Interface

PCI-AGP Bridge

B0:D1:F0

HL 11:0 HL_STB

DEVICE 1

DEVICE 0

AGP Bus

(PCI Bus 2)

ADDR DATA CTRL

Host Bus

Logical

PCI Bus 0

SBS[1:0]

SMA[12:1]

SCS[11:1]#

SWE#

SCAS#

SRAS#

System

Memory

Interface

SCB[7:0]

SDQ[63:0]

RDCLKIN

RDCLK0

AGP Slot

B2:D0:F0

DEVICE 0

BUS 0

BUS 0

BUS 2



82815 GMCH PCI Devices

Host-Hub Bridge

B0:D0:F0

Hub

Interface

PCI-AGP Bridge

B0:D1:F0

HL [11:0] HL_STB

DEVICE 1

DEVICE 0

AGP Bus

(PCI Bus 2)

ADDR DATA CTRL

Host Bus

Logical

PCI Bus 0

SBS[1:0]

SMA[12:1]

SCS[11:1]#

SWE#

SCAS#

SRAS#

System

Memory

Interface

SCB[7:0]

SDQ[63:0]

RDCLKIN

RDCLK0

AGP Slot

B2:D0:F0

DEVICE 0

BUS 0

BUS 0

BUS 2

Graphics

Accelerator

B0:D2:F0

DEVICE 2BUS 0Analog Display Out

Digital Video Out

Display Data

Channel



The ICH and MCH each contain PCI devices which are

designated with a 1 byte hex number--the ICH has three: Device 1E: Hub to PCI Bridge- Resides on PCI bus 0

Connects PCI bus 0 to PCI bus1 to extend outside the ICH

Device 1F: Multi-function- resides on PCI bus 0

PCI to LPC Bridge for interface to firmware hub and Super I/O

IDE controller

SMB controller

Two USB controllers

AC97 Audio Controller

AC97 Modem Controller

Device 08: LAN controller- Resides on PCI bus 1

Supports 10/100 Mbit/sec Ethernet and 1Mbit/sec Home PNA



ICH PCI Devices

Audio Ctr.

B0:D1F:F5

Modem Ctr

B0:D1F:F6

HUB-PCI Bridge

B0:D1E:F0

HubInterface

PCI-LPC Bridge

B0:D1F:F0

LAD [3:0]

LFRAME#

LDRQ[0:1]#

SMB Controller

B0:D1F:F3 SMBCLK

SMBDATA

LAN Cntr.

B1:D8:F0LAN_TXD[2:0]

LAN_RXD[2:0]

LAN_CLK

HL [11:0] HL_STB

DEVICE 1F

DEVICE 8

DEVICE 1ELogical

PCI Bus 0

AC97

Controller

AC_BIT_CLK

AC_SYNC

AC_RST#

AC_SDIN1

AC_SDIN0

AC_SDOUT

PCI Bus 1

USB Ctr. 2

B0:D1F:F4

USBP2[P:N]

USBP3[P:N]

OC[3:2]#

USB Ctr. 1B0:D1F:F2

USBP0[P:N]USBP1[P:N]

OC[1:0]#

PDCS1#

IDE Controller

B0:D1F:F1

PDA[2:1]

PDD[15:0]

PDDREQ

PDDACK#

PDIOR#

PDIOW#

PIORDY

BUS 1

BUS 0



ICH PCI Devices

Audio Ctr.

B0:D1F:F5

Modem CtrB0:D1F:F6

HUB-PCI BridgeB0:D1E:F0

Hub

Interface

PCI-LPC BridgeB0:D1F:F0

SMB ControllerB0:D1F:F3

LAN Cntr.B1:D8:F0

DEVICE 1F

DEVICE 8

DEVICE 1ELogical PCI

Bus 0

AC97Controller

PCI Bus 1

USB Ctr. 2B0:D1F:F4

USB Ctr. 1

B0:D1F:F2

IDE Controller

B0:D1F:F1

BUS 1

BUS 0

Chipset data books use DECIMAL numbers to identify

devices: e.g., Device 1Eh = 30(10) ;Device 1Fh = 31(10)

Bus:Dev:FN

(in decimal)Functional

Description

0 : 30 : 0 Hub-PCI Bridge

0 : 31 : 0 PCI-LPC Bridge

0 : 31 : 1 IDE Ctlr

0 : 31 : 2 USB Ctlr 1

0 : 31 : 3 SMBus Ctlr

0 : 31 : 4 USB Ctlr 2

0 : 31 : 5 Audio Ctlr

0 : 31 : 6 Modem Ctlr

1 : 8 : 0 LAN Ctlr

Chipset Data

Book Description



The MCH and ICH areconnected together by:

1: the PCI Bus

2: the LPC Bus

3: the Hublink Bus

4: the ISA Bus

3: the Hublink Bus

M-1



The FWH contains

512KB or 1MB of Flash ROM for storing BIOS code/dataArranged into 64KB lockable blocks

Block Lock Registers

One for each 64KB block to lock read or write ability

General Purpose Register

Reflects status of FGPI pins

Typical use of FGPI pins are to gather misc. data such as jumpersettings (BIOS recovery jumper)

Random Number Generator

Can produce Random Numbers used for data encryption

RNG mayormay notbe present (depends of version of FWH)



Firmware Hub (FWH)

LAD[3:0] / FWH[3:0] FWHInterface Flash

ROM

512KB

(1MB)Random

Number

Generator

LPC Bus

Block

Lock

Regs

ID[3:0]

FGPI[4:0]

General Purpose

Inputs

Device shown as used in FWH Mode

See chapter 3 for details on AAMux Mode

LFRAME / FWH4



LAN

Home networking

MODEM & DSL

Wireless

Audio

USB

The CNR provides the PC Industry the opportunity to

deliver a flexible and cost reduced method toimplement subsystems widely used in "connected PCs".

The CNR Specification is an open industry specification

and is supported by OEMs, IHV card manufacturers,

silicon suppliers and Microsoft. CNR Spec. calls for cards to be PnP: an EEPROM on

the CNR card contains configuration information.

Upper three SMB Address bits of CNR card determined

by pull up resistors on the system board.



OC

*USB1[P:N]

Audio Ctr.B0:D1F:F5

Modem Ctr

B0:D1F:F6

SMB Controller

B0:D1F:F3SMBCLK

SMBDATA

AC97

Controller

AC_BIT_CLK

AC_SYNC

AC_RST#

AC_SDIN1

AC_SDIN0

AC_SDOUT

USB Ctr. 2

B0:D1F:F4 * OC#

CNR

Connector

ICH

CNR Interface to ICH

LAN Cntr.

B1:D8:F0LAN_TXD[2:0]

LAN_RXD[2:0]

LAN_CLK

DEVICE 8BUS 1BUS 0

DEVICE 1F

+12v

+3.3v

-12v

* USB lines may alternatively be routed from USB Host Controller ASIC

SMB_A0

SMB_A1

SMB_A2

Used to strap

lower three

bits of CNRSMB Address(in this case: 110)

CNR

EEPROM

Interface

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

Used to

communicate

with EEPROM

on CNR card(see appendix)

+5v

+5v M-3



CNR Connector Pinout

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

RESERVED

RESERVED

RESERVED

GND

RESERVED

RESERVED

GND

LAN_TXD1

LAN_RSTSNC

GND

LAN_RXD2

LAN_RXD0

GNDRESERVED

+5Vdual

USB_OC#

GND

-12V

+3.3VD

KEY

GND

EE_DOUT

EE_SHCLK

GND

SMB_A0

SMB_SCL

CDC_DN_ENAB#

GND

AC97_SYNC

AC97_SDATA_OUT

AC97_BITCLK

RESERVED

RESERVED

GND

RESERVED

RESERVED

GND

LAN_TXD2

LAN_TXD0

GND

LAN_CLK

LAN_RXD1

RESERVED

USB+GND

USB

+12V

GND

+3.3Vdual

+5VD

KEY

GND

EE_DIN

EE_CS

SMB_A1

SMB_A2

SMB_SDA

AC97_RESET#

AC97_SDATA_IN2

AC97_SDATA_IN1

AC97_SDATA_IN0

GND

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A1



1) The FWH is accessed via the:

A) LPC Bus C) Hublink BusB) PCI Bus D) Beaverton-Hillsdale

Highway Bus

2) Which chip controls PCI Bus 1?

A) ICH C) FWHB) MCH D) SIO

3) The Intel Hublink Bus can transfer data at 3.2GB/s(True / False)

4) Which of the following devices is routed to the CNRconnector?

A) IDE controller C) AGP controller

B) Floppy controller D) Audio Controller

Chapter 1 QuizM-4



REVIEW & SUMMARY Intel Hub Architecture

Contains:MCH (GMCH in value PC applications)

ICH

FWH

Intel Hub Link Bus attributes

Can transfer data between the MCH and ICH at 266MB/s

Intel Proprietary



REVIEW & SUMMARYMCH and GMCH Control Memory and Graphics

MCH: AGP controller GMCH: Integrated Graphics Accelerator (Direct AGP)

ICH contains:

Hub to PCI Bridge

Connects PCI bus 0 to PCI bus1 to extend outside the ICH

PCI to LPC Bridge for interface to firmware hub andSuper I/O

IDE controller

SMB controller

Two USB controllers

AC97 Audio Controller

AC97 Modem Controller


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REVIEW & SUMMARYFirmware Hub

Contains BIOS Utilizes Flash ROM technology

Can be reprogrammed in place on the motherboard

Communications and Networking Riser

Interface to devices in ICH:

MODEM controller

Audio controller

USB controllerSMB Controller

End of Chapter 1

Documents

1 CS Bus Hub Arch Overview