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COMP541COMP541

State MachinesState Machines

Montek SinghMontek Singh

Feb 6, 2007Feb 6, 2007

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TopicsTopics How to design machines that go through a How to design machines that go through a

sequence of eventssequence of events Basically, close this loop:Basically, close this loop:

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Representation of Sequential CircuitsRepresentation of Sequential Circuits Earlier we learned how to specify Earlier we learned how to specify

combinational circuitscombinational circuits Truth tables, Boolean equations, …Truth tables, Boolean equations, …

Now extend to synchronous sequential circuitsNow extend to synchronous sequential circuits Include timeInclude time Use ‘state tables’ and ‘state diagrams’Use ‘state tables’ and ‘state diagrams’

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Input EquationsInput Equations Can describe inputs to FF with logic equationsCan describe inputs to FF with logic equations

)( BXAXDA

XADB

XBAY )(

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Time is ImpliedTime is Implied Note that last circuit used theNote that last circuit used the

Previous state to determine next statePrevious state to determine next state State and inputs to determine outputsState and inputs to determine outputs

Synchronous circuitSynchronous circuit So timing is discreteSo timing is discrete When are transitions?When are transitions?

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State TableState Table Just truth table with state addedJust truth table with state added

)( BXAXDA XADB XBAY )(

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Another TableAnother Table Same info, different layout styleSame info, different layout style

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Sequential Circuit TypesSequential Circuit Types

Moore model – Moore model – outputs depend outputs depend on stateson states

Mealy model – outputs Mealy model – outputs also depend on inputsalso depend on inputs

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State DiagramState Diagram Alternative representation for state tableAlternative representation for state table Moore:Moore:

State/OutputInputs

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Mealy ModelMealy Model Output depends on Output depends on

input and stateinput and state

Input/Output

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State Table vs. DiagramState Table vs. Diagram Same informationSame information Table is perhaps easier to fill in from Table is perhaps easier to fill in from

descriptiondescription Diagram is perhaps easier to understandDiagram is perhaps easier to understand

You can label states with English descriptionYou can label states with English description

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Design ProcedureDesign Procedure Take problem description and refine it into a Take problem description and refine it into a

state table or diagramstate table or diagram Assign codes to the statesAssign codes to the states Derive Boolean equations and implementDerive Boolean equations and implement

Or, write Verilog and compileOr, write Verilog and compileSee example next classSee example next classDesigning with gates and FFs more involved because you Designing with gates and FFs more involved because you

have to derive input and output functionshave to derive input and output functions

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Example – Sequence RecognizerExample – Sequence Recognizer Circuit has input, X, and output, ZCircuit has input, X, and output, Z Recognizes sequence 1101 on XRecognizes sequence 1101 on X

Specifically, if X has been 110 and next bit is 1, make Specifically, if X has been 110 and next bit is 1, make Z highZ high

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How to Design StatesHow to Design States States States rememberremember past history past history Clearly must remember we’ve seen 110 when Clearly must remember we’ve seen 110 when

next 1 comes alongnext 1 comes along

Tell me one necessary stateTell me one necessary state

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Beginning StateBeginning State Start state: let’s call it AStart state: let’s call it A If 1 appears, move to next state BIf 1 appears, move to next state B

Input / Output

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Second 1Second 1 New state, CNew state, C To reach C, must have seen 11To reach C, must have seen 11

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Next a 0Next a 0 If 110 has been received, go to DIf 110 has been received, go to D Next 1 will generate a 1 on output ZNext 1 will generate a 1 on output Z

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What else?What else? What happens to arrow on right?What happens to arrow on right? Must go to some state.Must go to some state. Where?Where?

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What Sequence?What Sequence? Here we have to interpret problemHere we have to interpret problem We’ve just seen 01We’ve just seen 01

Is this beginning of new 1101?Is this beginning of new 1101? Or do we need to start over w/ another 1?Or do we need to start over w/ another 1?

Textbook: decides that it’s beginning (01…)Textbook: decides that it’s beginning (01…)

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Cover every possibilityCover every possibility Well, must have every possibility out of every Well, must have every possibility out of every

statestate In this case, just two: X = 0 or 1In this case, just two: X = 0 or 1 You fill in other casesYou fill in other cases

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Fill inFill in

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Answer From BookAnswer From Book

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State MinimizationState Minimization When we make state diagram, do we need all When we make state diagram, do we need all

those states?those states? Some may be redundantSome may be redundant State minimization procedures can be usedState minimization procedures can be used

We won’t cover nowWe won’t cover now

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ReadingReading 7-1 and 7-117-1 and 7-11

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TodayToday Simple state machinesSimple state machines

How to code them in VerilogHow to code them in Verilog

Next ClassNext Class More on state machine stylesMore on state machine styles RegistersRegisters CountersCounters