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A NEW 12-bits 40 MS/s, LOW-POWER, LOW-AREA PELINE ADC FOR VIDEO ANALOG FRONT ENDS

班級 : 積體所碩一

學生 :林義傑

RCIM, Dept. of Electrical and Computer EngineeringUniversity of Windsor, Windsor, ON, N9B 3P4, Canada

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Reference

D. Dalton, G. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh, and P. Griffin,“A 200-MSPS 6-Bit Flash ADC in 0.6-μ m CMOS,” IEEE Trans. On Circuits and Systems-II, vol. 45, no. 11, pp. 1433-1444, Nov., 1998.

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Outline

The common Pipeline ADC The proposed pipeline Adc ArchetectureMeasurement ResultsConclusion

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ADC 應用頻率範圍及速度介紹

fs ≥ 2 fin

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Introduction common Pipeline ADC

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ADC 工作模式

Voltage-Mode

Current-Mode

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The proposed pipeline Adc Archetecture

fs ≥ 2 fin

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Current-mode stage architecture

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Current-mode stage architecture

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Power dissipation and area of each stage

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Measurement Results

SFDR=62.5dB

SNDR=58.3dB

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Measurement Results

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Conclusions

The proposed ADC architecture has

used a combination of current-mode

and voltage-mode stages to significantly reduce both power dissipation and area