1

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Figure 10.1 Truth table and schematic diagram for a binary half-adder.

10.1 Simple Adders

Half-adder

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Figure 10.2 Truth table and schematic diagram for a binary full adder.

Full-adder

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AddersHalf adder: add two digits without considering carry in.

ABCarryBABASum

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Full adder: add two digits and carry in.

CBACB)A()CBA(

CB)ABA(AB)CBA(

ABCCBACBACBASum

B)CAABB)CABAC)CAB(

CBABCAABCCABCout

((

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Figure 10.3 Full adder implemented with two half-adders, by means of two 4-input multiplexers, and as two-level gate network.

x y Ci

Co

S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

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Figure 10.4 Ripple-carry binary adder with 32-bit inputs and output.

Ripple-carry n-bit full-adder

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Figure 10.5 The main part of an adder is the carry network. The rest is just a set of gates to produce the g and p signals and the sum bits.

Carry Propagation Networks

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Figure 10.6 The carry propagation network of a ripple-carry adder.

ii

iiii

cp cyxs

iii

iiiii1i

cpg c)yx(yxc

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Speed up of carry propagation:

Provide a skip paths in a ripple-carry network.

1-4j1-4j1-4j4j cpgc

Carry equation remains the same for c4j, c4j+1, c4j+2, c4j+3, but c4j+4 different.

14j14j14j24j cpgc 24j24j24j34j cpgc

4j4j4j14j cpgc

4j4j14j24j34j34j34j34j44j cppppcpgc

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Figure 10.8 Driving analogy for carry propagation in adders with skip paths. Taking the freeway allows a driver who wants to travel a long distance to avoid excessive delays at many traffic lights.

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Figure 10.9 Schematic diagram of an initializable synchronous counter.

10.3 Counting and IncrementationNecessity: e.g., set a register to a value x, and repeatedly add a constant a. sequence values, x, x+1a, x+2a …

Full adder + additional circuit

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Figure 10.10 Carry propagation network and sum logic for an incrementer.

Incrementer: a =1

By setting cin=1, y=0, therefore,

iiiiiiiiii cxs ,xyxp 0,yxg

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• Brent-Kung carry lookahead network • [a, b]: stands for (g[a,b], p[a,b])• Carry operator : combines the generate and propagate signals for two

adjacent block[i+1,j] and [h,i] of digital positions into respective signals for wider block [h,j].

10.4 Design of Fast Adder

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iiiiii yxp yxg

G01 = G11 or ( P11 and G00 ) P01 = P11 and P00

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Figure 10.12 Brent-Kung lookahead carry network for an 8-digit adder, with only its top and bottom rows of carry operators shown.

8-input Brent-Kung network: composed of a 4-input Brent-kung network + two rows of carry operators.

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Blocks needed in the design of carry-lookahead adders with four-way grouping of bits.

00120121223

00101120001

0123[0,3]0123123233[0,3]

p g

cpppgppgpgccppgpgccpgc

ppppgpppgppgpg

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Figure 10.14 Carry-select addition principle.

Carry-select adderK-bit adder: one (k/2)-bit adder in lower half + two (k/2)-bit adders in the upper half.

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16 bit Brent-Kung Carry Lookahead Network

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16 bit Sklansky adder

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Figure 10.15 Multiplexer-based logical shifting unit.

10.5 Logic and Shift Operations

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Figure 10.16 The two arithmetic shift instructions of MiniMIPS.

Shift instruction in MiniMIPS: “shift right arithmetic ” and “shift right arithmetic variable”

sra $t0, $s1, 2 # set $t0 to ($1) right-shifted by 2srav $t0, $s1, $0 # set $t0 to ($1) right-shifted by ($s0)

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Figure 10.17 Multistage shifting in a barrel shifter.

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Figure 10.18 A 4 × 8 block of a black-and-white image represented as a 32-bit word.

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10.6 Multifunction ALU• ALU = adder + AND, OR, XOR, NOR gates• Example in Fig.10.19• (1) Arithmetic operation: F1F0=10

– (i) add/Sub = 0: x+y– (ii) add/Sub = 1; x-y = x+y’+1

• (2) Logic operation: F1F0=11, AND, OR, XOR, NOR• (3) Shifter

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Figure 10.19 A multifunction ALU with 8 control signals (2 for function class, 1 arithmetic, 3 shift, 2 logic) specifying the operation.