Vo1.12 No.1 JOURNAL OF ELECTRONICS Jan. 1995

0 .8~m L D D C M O S R E L I A B I L I T Y E X P E R I M E N T S A N D A N A L Y S I S

Yu Shan(~ I10 (Insti tute of Computer Application and Simulation Technology,)

Second Academy, Ministry of Aero-Space Industry, Beijlng 100854)

Zhang Dinglmng(~J~]~) Huang Cha~g(~ ~ )

(Shaanxi Microelectronics Institute, Lintong 710600)

A b s t r a c t The numerical simulation of two dimensional device is conducted to describe the

mechanism of the special substrate current and degradation of submicron LDD structure observed

in experiments, and finally, the optimum processes for submicron LDD CMOS axe proposed.

K e y w o r d s Submicron LDD device; Simulation; Reliability

I. Introduct ion

Because of its ability to effectively suppress the hot carrier effect and short channel

effect as well as improve the characteristics and reliability of devices, LDD (Lightly Doped

Drain)[ 1] structure is widely used in various kinds of submicron VLSI. However, the deep

investigation indicates that it is that the special lightly doped regions in LDD causes the

special degra~lation of LDD [2]. The lightly doped process should be optimized [3] so that the

side effects on devices can be reduced to minimum.

II. Devices F a b r i c a t i o n

Devices are fabricated in accordance with the CMOS process. P-well is built in p =

1-2 ft.cm, N-type Si suhstrate. PMOSFET is built in N-type substrate directly, while

NMOSFET is placed in P-well. The main process is as follows:

(1) After the N + polysilicon gate electrode is formed, PMOS LDD P - region is

completed by BF2 + implantation with doses of 7 x 1012 ~ 8 x 101a/cm 2 and energy of

25 ~ 60keV. For NMOS, Phosphorous is implanted to form N - region with conditions of

5 X 1012 ~ 9 • I013/cm 2, 30 ,-, 70keY;

(2) LPCVD 400nm SiO~. is followed by SiO2 reactive in etching with CHF3 as reactive

gas to form 0.20pro spacer;

(3) Implantation with spacer as mask may respectively form the N + and P+ doping.

N + region is implanted by arsenic and P+ region is implanted by BF2+;

(4) The last step of fabrication of LDD structure is annealing. The depth of N+/P junction is 0,20pro and that of P+/N junction is 0.35pro, as seen in Fig.1.

Thickness of the gate oxide is 28nm. Double ion implantation technology for P-channel

No.1 0.8pm LDD CMOS RELIABILITY E X P E R I M E N T S AND ANALYSIS 85

Polysilicon gate Si0= spacer

N~guba trate

Fig.1 The schematic of LDD CMOS

and medium energy boron implantation for N-channel are used to reduce the buried-channel

depth and short channel effect of devices respectively.

I I I . Test" R e s u l t s

1. S u b s t r a t e c u r r e n t

Fig.2(a) shows an abnormal rebound of substrate current when N-dose is 5 x 1012/cm 2

and Vg0 is relative high. It can be seen tha t the increase of N - implantat ion dose leads

to the increase of substrate current, however, when N - implantat ion energy goes high, the

substrate current goes small. Fig.3 also shows tha t when P - dose is 7 x 1012/cm 2 and P -

energy is 25keV with relative high Vg~, there is an abnormal rebound of substrate current,

and the higher implantation energy and dose are, the larger the substrate current is.

10-d

10 -s

lO_e

10 -7

10-t

10-4

10-$1

' ' ' ' ' ' ' " ' I N'- doses (a) 5 $ ~ 10: 3/cm 21

2.0 4.0 8.0 8.0 V., (V)(NM OS)

•E 10 -~

10_7

tO-S

] 0 - E �9 �9 , , = = = * *

0 I0 g

', i , 0 , i , 1 ,

N- energy (b)

3O 45

I | * t * �9 �9 �9 ,

2.0 4.0 6.0 8.0 V=, (V)(NMOS)

Fig.2 The gate-source voltage vs. substrate current under different N - implantation conditions

(NMOS) (Left = 0.80/~m, Vdo=SV, Kub=0) (a) N - implantation energy is 40keV; (b) N - implantation dose is 1 x 1013/cm 2

2. B u r n i n g c h a r a c t e r i s t i c s

Fig.4 and Fig.5 illustrate the burning characteristic curves of NMOS and PMOS respec-

tively. Fig.4 shows tha t when the burning t ime is relative short, LDD degrades faster than

conventional M O S F E T , and when P - imp|anta t ion dose and energy increase, the degra-

dation of LDD is relative slow. Fig.5 also indicates tha t the conventional device degrades

86 JOUR~IAL OF ELECTRONICS Vol.12

10 -e 8 8 0.7 x i 0 1 3 / c m

'~ 10-7

-.~ iO-e

lO-e

l O - t o

- - t i i ' i , i i

P- doses (a io -S

i , i , i . i �9

- - 2 . 0 .--4.0 --6.0 --8.0

V,, (V)(PMOS)

iO-S/ , , . , . , �9 , F (b)

10-61 P - energy

~" I O - ' ~ 6 0 40 2 5 k e y

.~ I0 -e

J lo-, F I O - I O l . ~ I , I I I i I

0 -2.0 -4 .0 -6.0 - 8 . 0 V,, (V)(PMOS)

Fig.3 The gate-source voltage vs substrate current under different P - implantation conditions

(NMOS) (Left = 0.80/zm, Vas=SV, Vsub~----~)

(a) P - implantation energy is 40keV; (b) P - implantation dose is 2 • 101Z/cm 2

much more than LDD does, and according to the increase of P - implantation energy and

dose, the degradation goes more as well.

I (a) (b)

1.o ~ t.o

0.11 ) ! O.l L i I I i I I I

10s, Imin lh 2h 3 10s Irnin ]h 2h 3h

Burning time Burning time

Fig.4 The burnln~ characteristics of NMOS with different N - implantation conditions (NMOS)

(L~ft = 0.80/Jm, Vd.=TV, Vu,=3V )

(a) N - implantation energy is 40keY; (b) N - implantation dose is 1 x 1013/cm 2

I V . T w o - D i m e n s i o n a l N u m e r i c a l D e v i c e S i m u l a t i o n a n d A n a l y s i s

Based on total quantity carrier analysis method, device simulation is conducted by

LADES-I two-dimensional numerical device simulation program to interpret the degradation

mechanism of LDD[4].

Fig.6 shows the electric field distribution simulation results of NMOS by LADES-I

two-dlmensional numerical device simulation program.

No.1 0.8#m LDD CMOS R E L I A B I L I T Y E X P E R I M E N T S AND ANALYSIS 87

tO

1.0 J

0.1

CON (a)

~ m z ) I ! I

los Imin lh 2h 3h

I

l~ I (b}

1,0 60 40 25 keV

10s lmin lh 2h 3h Burning time Barning time

Fig.5 The burning characteristics of NMOS with different P - implmntation conditions (NMOS)

(Lea"----O.80pm, Vd,=--5V, Va,=-2V)

(a) P - implantation energy is 40keY; (b) P - implantation dose is 2 x 1013 / cm 2

The phenomena of Fig.2 can be explained as follows: the substrate current goes up while

N - dose increasing is due to the increase of drain region electric field(which can be seen in

Fig.6(a)). When Vg, is relative high and N - close is 5 x 1012/cm2, as shown in Fig.6(a), there

is an electric field crest at source region which results in the substrate current rebound as

shown in Fig.2(a). The higher N - implantation energy results in smaller substrate current,

which is shown in Fig.2(b), it is due to the electric field crest going deeper into silicon, and

as the carriers mainly flow through near the silicon surface, collision ionization is decreased.

N- doses e.o Io CoN j (a)]'

Io 2 x 1013/cm z 5.0 In 5x 10re/cm ~

I 4.0 ~ VR, =7.OV f ~

--- V,, = 2.0V s.0 I I o

l / , f i 2.0 1 II , , ,L /"

o

N + Channel N ~ . . . . . . . . , w-

CON,N§ ~ N*CON.

6.0 ~"

S.O l / ~ (b)

Jl CON

I

2 x 10 z 3/cm~.../~/ V,. =7V 1/ / [ i / /

I 0'5x 1013tcm2 ] V,, = 2V

N + ~ h a n n e l ~ " + - N ~

CON,N* N*,CON

4.0

:> 3.0

x 2.0

1.0

Fig.6 The electric field distribution of NMOS (Loft = 0.80pm, N- implantation energy is 45keV)

(~) Vd,=5.0V; (b) V~,=Z.0V

Because the N - region in LDD makes the electric field crest closer to the gate fringe

and even beyond the gate, as seen in Fig.6, when electric field produces collision ionization

88 JOURNAL OF ELECTRONICS Vol.12

which gives rise in the hot electron injection into the SiO2 at the N - region surface and

the trapped minus charge, which makes N - region resistance increase and /dO decrease,

the results in Fig.4 are explained. The reason why the smaller the N - implantation, the

more degradation in Fig.4(a) is that the smaller the N - implantation is, the further the

electric field goes beyond the gate, which makes the more produced hot electrons inject

into SiO2 at the N - surface, and that even if fewer minus charge is trapped into the SiO2

at the N - surface, the low impurity concentration of N - region can make N - resistance

greatly increase. The slowly degradation of LDD in Fig.4(b) is due to the fact tha t electric

field crest goes deeper into the silicon sudace and the probability of hot electron injection

into the SiO2 at N - surface goes smaller when N - implantation energy goes higher. For

conventional devices, as its electric field crest is within its gate (seen in Fig.6), and the hot

carriers produced by collision ionization mainly inject into the gate which causes channel

hot carriers effects, so devices degradation occurs. The hot carriers trapped in gate oxide is

more and more when the stress time becomes long, and as the electric field of conventional

devices is higher than that of LDD, the speed of trapping hot carriers is much faster. Because

part of hot carriers trapped into gate oxide becomes gate current and another part becomes

trapped charge which has effective effect on mobility of the carriers which effect on current

is not so et~cient as direct increase N - resistance of LDD, when stress time is short, LDD

degrades more than Conventional device, and when stress time is long, Conventional device.

degrades more than LDD, which indicates that LDD is still more reliable and has longer life

than conventional device d0esls].

The case of PMOS is somehow different f~om that of NMOS. When IV981 is relative

high and P - concentration is low (the dose and energy of P - are 7 x 1012/cm 2 and 25keV

respectively), LADES-I simulation indicates that there is an electric field crest at the source

end which causes abnormal substrate current phenomena as seen in Fig.3. The higher P -

implantation dose and energy axe, the smaller P - resistance and the higher electric field at

the drain end are, and this electric field causes a larger substrate current. The main reason

is that PMOS is a buried-channel device. Because PMOS has a special HEIP effect(Hot-

Carrier-lnduced Punchthrough Effect) [el, the higher P- implantation dose and energy are,

the higher electric field at the drain end is, then the heavier HEIP effect is, and the more

/do increases. This is the reason that conventional PMOS degrades faster than LDD PMOS.

V. Conc lus ions

According to the experimental data and analysis above, LDD can reduce drain electric

field and suppress hot carriers effect efficiently, as well as makes devices longer life and more

reliable, but LDD has a particular hot carrier effect which makes device degrade, so that its

lightly-doped process must be optimized to suppress its disadvantages.

For NMOS, considering that the other characteristics of devices [7], the optimum LDD

N - implantation dose and energy axe I ~ 3 x 101S/cm 2 and 45keV respectively in this

experiment.

No.1 0 .8#m L D D C M O S R E L I A B I L I T Y E X P E R I M E N T S A N D A N A L Y S I S 89

For P M O S , analysis in the same wa y as NMOS, the o p t i m u m L D D P - implan ta t ion

dose and energy which are 2 • 101a /cm 2 and 40keV respect ively axe ob ta ined in this exper-

iment.

The o p t i m u m condit ions men t ioned above have been appl ied to some ICs fabr icat ion

including 0.50pro C M O S vol tage-control led oscillator circuit whose main f requency is over

600MHz and gate delay is 130ps wi th yield a b o u t 15 percent Is], and 1 .0#m bus exchange

logic circuit whose main f requency is over 20MHz with yield abou t 30 percent [9].

R e f e r e n c e s

[1] s. Ogura, P. J. Tsang, W. W. Walker et al., IEEE Trans. on El), ED-27(1980)8, 1359-1367.

[2] J. Hui, F-C. Hsu, J. Mo/], IEEE Electron Device Lett. 6(1985)3, 135-138.

[3] F-C. Hsu, K. Y. Chin, IEEE Electron Device Lett. 5(1984)5, 162-165.

[4] Du Ming, Huang Chang, Chinese Journal o f Semiconductors, 9(1988)1, 1-6 (in Chinese).

{5] P. N. Andhaxe, R. K. Nahar, N. M. Devashrayee et al., Microelectronics Re//ab., 30(1990)4, 681-690.

[6] M. Koyanagi, A. G. Lewis, R. A. Martin et al., IEEE Trans. on ED, ED-34(1987)4, 839-844.

[7] Yu Shan, Zhang Dingkang, Huang Chang, Chinese Journal of Semiconductors, 13(1992)7, 423-429 (in

Chinese).

[8] Yu Shah, Zhang Dingkang, Huang Chang, "Development of 0.50#m CMOS Integrated Circuits Tech-

nology", Proc. of 3rd ICSICT. Beijing: 1992, 143-146.

[9] Yu Shan, Zhang Dingkang, Huang Chang, "l/~m High Speed LDD CMOS Titanium Silicide Bus Ex-

change Logic Integrated Circuit", Proc. of The First National Conference on Applications in Special

Integrated Circuits(ASIC) of China. Wuxi: 1990, 203-204 (in Chinese).