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Enhanced Bias-flip Rectifier with Ultra-Low Power

control for Piezo Electric Energy Harvester in the

Microwatt Application Scenario

Ramesh Vaddi1, and S. Dasgupta21Electronics and Communication Engineering Department, Padmasri Dr. B. V. Raju Institute of Technology, Hyderabad, India

2Electronics and Computer Engineering Department, Indian Institute of Technology Roorkee, Uttarakhand-247667, India

AbstractLow power devices promote the development of micropower generators (MPGs). There is an increasing interest in

harvesting ambient vibration energy through piezoelectric means

by which one can potentially draw 10100s of W of available

power. The limitations of existing piezoelectric harvesters is in

their interface circuitry consuming large power and also large

amount of charge getting wasted in charging and discharging

large capacitance associated with the piezo device . In this paper,

an enhanced bias-flip rectifier topology that can improve thepower extraction capability from piezoelectric harvesters is

presented. It has been shown that the proposed rectifier topology

has 4X more output power over conventional full-bridge

rectifiers and voltagedoublers and 3.25 times maximum output

power in comparison to existing bias-flip topology. The proposed

interface circuitry consumes ultra low power (less than 6W)

and achieves a near ideal inversion coefficient required for the

perfect bias flipping.

Keywords- Micropower generators, Microwatt applications,

Piezo electric energy harvesting; Ultra-low power.

I. INTRODUCTIONThe dependence on the battery as the only power source is

putting an enormous burden in emerging applications such as

wireless micro-sensor networks [1], implantable medical

electronics, tire-pressure sensor systems [2] and several

personal digital assistants (PDAs) etc. It is often impractical to

operate these systems on a fixed energy source like a battery

owing to the difficulty in replacing the battery. For example, a

1 cm3 primary lithium battery has a typical energy storage

capacity of 2800J [3]. This can potentially supply an averageelectrical load of 100 W for close to a year but is insufficient

for systems where battery replacement is not an easy option.

The ability to harvest ambient energy through energy

scavenging technologies is necessary for battery-less

operation. An attractive alternative to batteries is micro powergenerators (MPGs), which have recently gained increasedattention. An MPG is expected to be five-to-ten times smaller

than a comparable battery, and features enhanced

performance. The most common harvesters transduce solar,

vibrational or thermal energy into electrical energy.

Harvesting ambient vibration energy through piezoelectric

(PE) means is a popular energy harvesting technique whichcan potentially supply 10100s of W of available power [3].

This low power output necessitates not only the design of

ultra-low power control circuits but also efficient power

delivery interface circuits that can extract the maximum power

available out of the energy harvesters. Commonly used full-

bridge rectifiers and voltage doublers [4] severely limit the

electrical power extractable from a PE harvesting element.

Further, the power consumed in the control circuits reduces

the amount of usable electrical power. G. K. Ottman, et al, in[5], [6] propose and derived analytical expressions for the

optimal power flow from a rectified piezoelectric device andpropose adaptive control techniques for the dcdc converter

(but for a full bridge rectifier topology). In [7], the authors

fabricate and test various interface circuits to the piezoelectric

MPG such as half-wave synchronous rectifier with voltagedoubler, a full-wave synchronous rectifier and passive full-

wave rectifier etc, and demonstrate a peak power of 22 W.

In [8]-[10], the authors propose various piezoelectric

architectures utilizing buck-boost converter [9] and adaptive

stand alone system [10] for maximum power extraction. It has

been recently demonstrated that utilizing non-lineartechniques such as synchronous switch harvesting on inductor

(SSHI) (serial SSHI and parallel SSHI) [11]-[15], synchronous

electric charge extraction (SECE) [16], double synchronousswitch harvesting (DSSH) etc, one can extract significantly

more power from a piezoelectric generator in comparison to

conventional topologies. Y. K. Ramadass, et al, [18]-[20]

compare various rectifier topologies and propose an ultra low

power bias flip rectifier for a piezoelectric harvester. In this

paper, we propose an enhanced bias flip rectifier with ultra

low power control circuitry and increased power extraction

from the piezo MPG. The paper is organized as follows. In

section II, the theoretical background and various rectifier

topologies are summarized. Section III presents the proposed

rectifier topology and its power extraction. Simulation results

and discussion are presented in section III. Finally,

conclusions are offered in section IV.

II. THEORETICAL BACKGROUND AND VARIOUS RECTIFIERTOPOLOGIES AND PROPOSED RECTIFIER TOPOLOGY

A. Existing Rectifier topologies for Piezo Energy harvesting:A piezoelectric harvester is usually represented electrically

as a current source in parallel with a capacitor and resistor

(Fig. 1) [18-20]. The current source provides current

proportional to the input vibration amplitude. The current is

represented as ip=Ip Sinwpt, where wp=2 fp t, and fp is the

2012 Asia Pacific Conference on Postgraduate Research

in Microelectronics & Electronics (PRIMEASIA) 132

BITS Pilani Hyderabad Campus 5th - 7th December 2012

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frequency with which the piezoelectric harvester is excited.

The power output by the piezoelectric harvester can not bedirectly usable by load circuits such as micro-controllers,radios etc. The power conditioning and converting circuits

should also be able to extract the maximum power available

out of the piezoelectric energy harvester. Since the

piezoelectric harvester outputs a sinusoidal current, it first

needs to be rectified before it can be used to power circuits.

Fig. 1. Equivalent circuit of a piezoelectric energy harvester showing themechanical and electrical sides of the device.

Fig. 2. A full-bridge rectifier to extract power from a piezoelectric energy

harvester.

Fig. 3. A voltage doubler circuit to extract power from a piezoelectric energy

harvester.

Fig. 4. A Switch only rectifier to extract power from a piezoelectric energy

harvester [18-20].

Fig. 5. A Bias- flip rectifier to extract power from a piezoelectric energy

harvester [18-20].

Full-bridge and voltage doublers are the commonly used

rectifier topologies to convert the AC output of a piezoelectric

harvester into a DC voltage (Fig. 2 and Fig. 3). In the presenceof ideal diodes, the maximum power obtained by using a

voltage doubler is the same as that obtained using a full-bridge

rectifier. The voltage doubler however helps in pushing the

voltage at which the maximum is obtained up by 2X. In the

presence of diode non-idealities, the voltage doubler gives an

improvement in the overall power obtained. The maximumtheoretical conversion efficiency of both the topologies is very

less (12.5%) [18]. In [18-20], the authors propose a switch

only rectifier and a bias flip rectifier topologies as shown in

Fig. 4 and Fig. 5.

The voltage doubler provides current to the output only

during the positive half-cycle of iP. During the negative half-cycle, its parallel diode helps in pre-discharging CPto ground.

This way during the positive half-cycle, iP only needs to do

half the work to charge up CPto VRECTbefore it can flow into

the output. We actually dont need to spend an entire half-

cycle just to discharge CPto ground. This is addressed by the

switch-only rectifier where a simple switch M1 is connected

across the piezoelectric harvester driving a full-bridge

rectifier. When the switch is ON, it discharges the capacitor CP

immediately to ground. Once CP has been discharged, M1 is

turned OFF. This frees up the rectifier to conduct during both

the half-cycles of the input current. The switch-only rectifierin effect works similar to two voltage doublers of opposite

phase working in tandem. With the addition of a simple

switch, the switch-only rectifier is able to provide 2X the

amount of electrical power that was provided

by the full-bridge rectifier or the voltage doubler.

The switch-only rectifier was able to utilize both half-cycles of the input current. However, there was still significant

amount of charge lost in the rectifier due to charging CP up

from 0 to VRECT every half-cycle. Fig. 5 shows the circuit

implementation of a bias-flip rectifier. Compared to the

switch-only rectifier, an additional inductor (LBF) has been

added in series with the switch M1. An inductor can passivelyflip the voltage across a capacitor. So instead of just using a

switch, the bias-flip rectifier utilizes an inductor to flip the

voltage across CP. The bias-flip rectifier provides 3.29X

improvement over the full-bridge rectifier.

III. PROPOSED RECTIFIER TOPOLOGY AND ITS POWEREXTRACTION

The proposed enhanced bias-flip rectifier topology is shownin Fig. 6. Compared to the bias-flip rectifier, an additionalsmall capacitor (CBF) has been added in series with the switchand inductor. At every half-cycle, when iPchanges direction,the switch S1 is turned ON briefly to allow the inductor to flipthe voltage across CP. The switch is turned OFF when thecurrent in the inductor reaches zero. The voltage flipping

becomes closer to perfect by adding a small capacitor CBF inseries The inversion process is characterized by Inversioncoefficient ( ), giving the ratio of absolute voltages beforeand after the inversion. For perfect bias flipping, will becloser to one. To derive the amount of output power extractable




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Fig.6. Proposed Enhanced Bias- flip rectifier to extract power from apiezoelectric energy harvester.

using enhanced bias-flip rectifier topology, let us assume thatthe resistance along the LBF, CP, CBFpath is RBF.Following theanalysis similar to [19], the power output by the bias-fliprectifier can be given by

2 2 ( )F

RECT P RECT P P F I

P

kV

P C V f V V V Q

=

Where VP is the open circuit voltage of the piezo generatorand

( )2 20

0

2

1 1 1

1

1

2

( 2 )

2

1

( ( 2 ) )

( 2 ) ( 2 )

( 2 )(1 )1

F RECT D

I RECT D

BF

BF

P BFBF

P BF

P RECT D p P p p

RECT D RECT D

RECT Dp

P

V V V

V V V e

w

R

L

w w

wC C

LC C

V V V e w t V Sinw t w t k

V V V V

V V ew t Cos

V

= +

= +

=

=

=

=

+

+ +

= +

+ +

+ =

There are three ways in which we can enhance (=e

-) value

of the bias-flipping circuit. Table I summarizes the

improvement in value by increasing LBF. Increasing LBF

although increases value, but we cant increase it too large

due to the requirement of large size off - chip inductor.

Another way, we can improve value is by reducing RBF asshown in Table II. Although, reducing series resistance RBFof

the loop improves, we cant reduce it below a limit due to the

process limitations. Therefore, another efficient manner in

which it can be improved is by placing a small capacitor (CBF)

in series with LBFas shown in Table III.

IV. SIMULATIONRESULTSANDDISCUSSIONThe proposed topology along with existing topologies are

designed and simulated in Cadence Virtuoso. The piezo device

model parameters used for simulations are IP=40A,

fP=225Hz,CP=10nf, RP=1M [19]. CMOS implementation of

the proposed rectifier topology in Cadence is shown in Fig. 7.

The switches are implemented using NMOS transistors. It was

discussed that the bias-flip switches are turned ON when the

current iPfrom the harvester crosses zero. Also, it is essential

to keep the switches ON for just enough time to achieve zero-

current switching of the inductor current. The diodes used in

the rectifier were obtained with synchronous rectifiers [21]

that use MOS transistors to replace the diodes. These have

much lower forward voltage loss compared to p-n junction

diodes or transistor-based diodes. Further detailed CMOS

implementation of internal blocks are given in [18]. Fig.8

shows the block diagrammatic representation of the controlcircuitry that determines the timing and gate-overdrive control

of the switches in the bias-flip rectifier. The switches need to

be turned ON when iPcrosses zero. When iP is close to zero,

the diodes are just on the verge of turning OFF. At this point

one of the voltages VHARP or VHARNis close to VRECT + VDand

the other one is close to VD. The zero-crossing of iP is

detected by comparing either VHARP or VHARNwith a reference

voltage VDREF. This comparison is done using a continuous-

RECT

Full Bridge

S1

VREC

T

IP CP

C

RP

LB

F

D1

D3

D2

D4

Piezo Harvester

Enhanced Bias-flip Rectifier

CBF

Table I: Improving Inversion coefficient by increasing LBF(CBF= 12nf, RBF= 26).

LBF(H)

22 0.367

47 0.513

82 0.606

820 0.855

Table II: Improving Inversion coefficient by minimizing RBF

(CBF= 12nf, LBF=47H).RBF()

50 0.254

40 0.346

30 0.46

26 0.513

20 0.601

15 0.684

10 0.777

Table III: Improving Inversion coefficient by placing smallCBFin series with LBF (LBF=47H, RBF= 26).

CBF nf)

120 0.53

12 0.6271 0.834

0.1 0.942

0.01 0.981

0.001 0.994

LBF=82 H,

CBF=0.001nf

0.995




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time comparator similar to the one in [18]. Table IV

summarize the power consumption of various control blocks

and it is observed that the total control circuitry power is less

than 6w (ultra low power), thus increasing the power

usability by the external load.

Fig.7. CMOS implementation of the Proposed Enhanced Bias- flip rectifier along with control circuitry to extract power from a piezoelectric energy harvester.

Fig. 9 presents a comparison of power extracted by the existingrectifier topologies with the proposed enhanced bias- fliprectifier topology. At a given rectifier voltage, say at 1V, thefull bridge rectifier has an output power of 7.8 w, voltage

doubler has an output power of 9.3 w, switch only rectifierhas an output power of 17.3, bias- flip rectifier has an output

power of 21.5 w and the proposed enhanced bias- flip rectifier

Fig.8. Block diagrammatic representation of the circuit for timing andgate-overdrive control of the enhanced bias-flip rectifier.

Table IV: Detailed power consumption of various control circuits

in the piezo architecture.

Block nameCurrent

(A)Power(W)

No. ofBlocks

Total

controlpower

(W)

Synchronous

Rectification Diode0.054 0.378 4 1.512

SynchronousRectification Diode

(biasing)

0.5 3.5 1 3.5

Zero Crossing

Comparator

0.09176 0.165168 1 0.165168

Zero Crossing

Comparator (biasing)0.349 0.6282 1 0.6282

Pulse Generator 0.000037 0.0000666 1 0.0000666

Level Shifter 0.000012 0.0000216 1 0.0000216

Non-overlapping

clock Generator0.000136 0.000816 1 0.000816

Gate OverdriveCircuit

0.0024 0.0144 1 0.0144

Total 5.82




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has an output power of 26.4 w. For given conditions, it canalso be observed that the maximum rectified output power ofthe proposed enhanced bias- flip rectifier is nearly 130 w,where as that of the bias-flip topology has 40 w andconventional full bridge topology has around 10 w. Fig. 10shows the power extracted by the proposed enhanced bias- fliprectifier for increasing bias-flip inductor sizes. It can beobserved that increasing the bias- flip inductor size has positive

effect on the increment in the maximum rectified output power,but this effect gradually diminishes a the size becomes toolarge. This is due to the fact that the inversion coefficient

becomes almost saturated and changes very less once theinductor size increases significantly and the effect will bealmost negligible after certain value, which is also not

preferable from the chip area and cost point of view.

V. CONCLUSIONIn this paper, an enhanced bias-flip rectifier topology with ultralow power control circuitry for extracting maximum output

power from a piezo energy harvester has been proposed. It hasbeen demonstrated that the proposed rectifier topology

significantly increases the maximum rectified output power.For a given piezo device model parameters and load condition,it has been observed that the maximum rectified output powerof the proposed enhanced bias- flip rectifier reaches nearly 130w, where as that of the existing bias-flip rectifier topology has40 w and the conventional full bridge rectifier topology hasaround 10 w. It has been also shown that the additionalcontrol circuitry required for enhanced bias- flipping requiresonly around 6 w of power generated (4.6% of maximum

power), thus increasing the usable power by the load circuitry.

ACKNOWLEDGEMENT

The authors would like to thank the technical support given byProf. Tony T. H. Kim and A. Thu Linn, School of EEE,

Nanyang Technological University, Singapore.

REFERENCES

[1] B. Calhoun, D. Daly, N. Verma, D. Finchelstein, D. Wentzloff, A.Wang, S.-H. Cho, and A. Chandrakasan, Design considerations forultra-low energy wireless microsensor nodes, IEEE Trans. Comput.,vol. 54, no. 6, pp. 727740, Jun. 2005.

[2] M. Seeman, S. Sanders, and J. Rabaey, An ultra-low-power powermanagement IC for wireless sensor nodes, in Proc. IEEE CustomIntegratedCircuits Conf., Sep. 2007, pp. 567570.

[3] S. Roundy, P. Wright, and J. Rabaey, Energy Scavenging for WirelessSensor NetworksWith Special Focus on Vibrations. Boston, MA:Kluwer Academic, 2003.

[4] T. Le, J. Han, A. von Jouanne, K. Mayaram, and T. Fiez, Piezoelectricmicro-power generation interface circuits,IEEE J. Solid-State Circuits,vol. 41, no. 6, pp. 14111420, Jun. 2006.

[5] G. K. Ottman, H. F. Hofmann, A. C. Bhatt, and G. A. Lesieutre,Adaptive piezoelectric energy harvesting circuit for wireless remotepower supply,IEEE Trans. Power Electron., vol. 17, no. 5, pp. 669676, Sep. 2002

[6] G. K. Ottman, H. F. Hofmann, and G. A. Lesieutre, Optimizedpiezoelectric energy harvesting circuit using step-down converter indiscontinuous conduction mode,IEEE Trans. Power Electron., vol. 18,no. 2, pp. 696703, Mar. 2003.

[7] T. T. Le, J. Han, A. Jouanne, K. Mayaram, and T. S. Fiez, Piezoelectricmicro-power generation interface circuits,IEEE J. Solid-State Circuits,vol. 41, no. 6, pp. 14111420, Jun. 2006.

[8] J. Han, A. V. Jouanne, T. Le, K. Mayaram, and T. S. Fiez, NovelPower Conditioning Circuits for Piezoelectric Micro Power Generators,19thIEEE Applied Power Electronics Conference and Exposition, Vol.3,pp. 1541 1546, 2004.

[9] E. Lefeuvre, D. Audigier, C. Richard, and D. Guyomar, Buckboostconverter for sensorless power optimization of piezoelectric energyharvester,IEEE Trans. Power Electron., vol. 22, no. 5, pp. 20182025,Sep. 2007.

[10] A. Tabesh, and L. G. Frchette, " A Low-Power Stand-Alone AdaptiveCircuit for Harvesting Energy From a Piezoelectric MicropowerGenerator," IEEE Trans. Industrial Electron., Vol 57, No 3, pp.840-849,March.2010.

[11] D. Guyomar, A. Badel, E. Lefeuvre, and C. Richard, Toward energyharvesting using active materials and conversion improvement bynonlinear processing, IEEE Trans. Ultrason., Ferro electr., Freq.Control, vol. 52, no. 4, pp. 584595, Apr. 2005.

[12] L. Garbuio, M. Lallart, D. Guyomar, and C. Richard, " MechanicalEnergy Harvester with Ultra-Low Threshold Rectification Based onSSHI Non-Linear Technique", IEEE Trans. Indus. Elec., Vol. 56(4),048-1056, 2009.

Fig. 9. Comparison between power extraction capabilities of existing

rectifier topologies and proposed enhanced bias-flip rectifier.

Fig. 10. Power extraction from the proposed enhanced bias-flip rectifier

for various bias-flip inductor values.




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[13] D. Guyomar, and M. Lallart, "Nonlinear Conversion Enhancement forEfficient Piezoelectric Electrical Generators", Ferroelectrics, Intechpublishers, pp.357-380,2010.

[14] M. Lallart, L. Garbuio, C. Richard, and D. Guyomar, " Low-CostCapacitor Voltage Inverter for Outstanding Performance in PiezoelectricEnergy Harvesting" IEEE Trans. Ultrason., Ferro electr., Freq.Control, vol. 57, no. 2, pp. 281-291, Feb. 2010.

[15] X. D. Do, Y. H. Ko, H. H. Nguyen, H. B. Le, and S. G. Lee, " Anefficient parallel SSHI rectifier for piezoelectric energy scavenging

systems ", 13th IEEE ICACT, 2011,pp. 1394 -1397.[16] T. Paing, and R. Zane, "Design and Optimization of an Adaptive Non-

Linear Piezoelectric Energy Harvester", 26th IEEE APEC, 2011,pp.412-418.

[17] M. Lallart, L. Garbuio, L. Petit, C. Richard, and D. Guyomar, Doublesynchronized switch harvesting (DSSH): A new energy harvestingscheme for efficient energy extraction, IEEE Trans. Ultrason.Ferroelectr. Freq. Control, vol. 55, no. 10, pp. 21192131, Oct. 2008.

[18] Y. K. Ramadass, Energy processing circuits for low-powerapplications,Ph.D. dissertation, Massachusetts Institute of Technology,Cambridge, MA, June. 2009.

[19] Y. K. Ramadass, and A. P. Chandrakasan, An Efficient PiezoelectricEnergy Harvesting Interface Circuit Using a Bias-Flip Rectifier andShared Inductor", IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 189204, Jan. 2010.

[20] Y. K. Ramadass, and A. P. Chandrakasan, An efficient piezoelectricenergy-harvesting interface circuit using a bias-flip rectifier and shared

inductor, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers,Feb.2009,pp.296297.

[21]N. Guilar, R. Amirtharajah, and P. Hurst, A Full-Wave Rectifier forInterfacing with Multi-Phase Piezoelectric Energy Harvesters, IEEEInt. Solid-State Circuits Conf. Dig.Tech. Papers, pp. 302615, Feb.2008.




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