05427010

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 1, JANUARY 2011 221

Robust and Fast Three-Phase PLL Tracking SystemFelice Liccardo, Pompeo Marino, and Giuliano Raimondo

Abstract—This paper presents a simple, robust, and fast syn-chronization method to detect the phase angle of the positivesequence of a three-phase ac system. The algorithm was derivedfrom a standard phase-locked-loop (PLL) circuit based on the pqtheory, but a feedforward action is implemented to guarantee highdynamic performance in conjunction with a modified feedbackaction to reduce the phase-angle estimation error to zero. Theresult is a fast tracking system that improves the start-up stageand rapid input variations. It guarantees accurate phase lockingand is robust with respect to ac distortions such as harmonics,subharmonics, and voltage imbalance. The control model for theproposed PLL system was based on the standard qPLL structure.A linear analysis was performed to show the benefits of theproposed solution, and recommendations are given for tuning itsparameters. The proposed technique was tested and comparedwith other algorithms by means of simulations. The experimentaland simulation results are shown and compared.

Index Terms—Phase-locked loop (PLL), power systems, syn-chronization, utility interface.

I. INTRODUCTION

THE growing use of static converters in both three- andsingle-phase applications requires a fast and accurate

method for phase-angle estimation. This is a very importanttask in any application where active/reactive power flow controlis needed. This control should guarantee the good operationof the power-conditioning equipment connected to the utilitygrid, such as an active front end (AFE), active filters, staticVAR compensator, uninterruptible power supply, flexible actransmission systems, etc. [1]–[6].

The wide diffusion of distributed generation (DG) units inelectric networks has required the large use and improvementof synchronization algorithms to detect the positive sequencecomponent of the utility network. In fact, when used as a windgenerator unit, photovoltaic-based unit, or microturbine gen-erator unit, a converter-interfaced DG unit requires convertersynchronization under a polluted and/or variable-frequencyenvironment, both in grid-connected and microgrid (islanding)configurations [7]–[13]. Moreover, due to the high numberof loads connected to a grid and the continuous variation ofnetwork conditions, the synchronization process should be fastand robust. These performances guarantee disturbance rejectionand fast algorithm convergence.

Hence, an ideal synchronization algorithm should detect thephase angle of the positive sequence of the voltage system, with

Manuscript received July 31, 2009; revised January 12, 2010; acceptedFebruary 16, 2010. Date of publication March 8, 2010; date of current versionDecember 10, 2010.

The authors are with the Dipartimento di Ingegneria dell’Informazione,Second University of Naples, 81031 Aversa, Italy (e-mail: [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2010.2044735

Fig. 1. Basic PLL structure.

the ability to track the phase and frequency variations even if thesupply voltages are distorted and unbalanced.

Various phase-detecting methods have been proposed[14]–[16]. The simplest, but not the most accurate methodunder nonideal conditions, is the zero-crossing strategy. Evenif they are better than the zero-crossing method, techniquesbased on low-pass filters (LPFs), space vector filters (SVFs), therecursive weighted least-square estimation algorithm, Kalmanfilters, or the fast Fourier transform do not have the bestperformance under polluted supply conditions. Other methodsfor managing the frequency and amplitude variations are basedon the concept of the adaptive notch filter (ANF).

The phase-looked-loop (PLL) technique, based on the syn-chronous reference frame (SRF), is the most comprehensivemethod under polluted supply conditions [17]–[23]. The basicscheme of the conventional PLL method is shown in Fig. 1. Thesimplicity of this structure makes this synchronization methodthe most widely accepted solution, owing to the simple analogand digital implementations. Based on a feedback structure andthe theory of dq transformations [1], a classical PLL struc-ture comprises a phase detector, loop filter (LF), and voltage-controlled oscillator. These structures have good performanceeven with signals affected by harmonics, interharmonics, volt-age sags, swells, and notches. On the other hand, they start topresent disadvantages in unbalanced operating conditions. Inthe literature, various kinds of PLL methods have been tried toovercome the aforementioned problems, such as enhanced PLL(EPLL) and decoupled double SRF PLL. These methods arecomplicated compared with the conventional PLL system, andwhen the signal is distorted by harmonics, the bandwidth shouldbe reduced, thus increasing the time response. Moreover, thestart-up stage does not have a good dynamic response.

Three-phase PLL systems based on Akagi’s instantaneouspower pq theory [24],[25] have been intensely studied an-alytically and experimentally, under both asymmetrical anddistorted supply conditions. The design criteria have also beenanalyzed to tune their parameters. These PLL systems areclassified as pPLL and qPLL.

A modified classical qPLL closed-loop structure incorporat-ing a feedforward action was presented and simulated in [26].This feedforward action guarantees high dynamic estimation

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222 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 1, JANUARY 2011

Fig. 2. qPLL system.

performance and the reduction of the residual estimation errorto zero.

This paper can be considered to be an extension of [26]. Itintroduces and analyzes the effect of the frequency variation onthe proposed solution, showing the good performances obtainedduring start-up under all input conditions and providing a com-plete linear analysis of the system stability in order to defineaccurate controller parameter design criteria. Moreover, nu-merical results have been obtained by comparing the proposedtechnique with the standard qPLL algorithm and recent syn-chronization techniques proposed in literature. Experimentalverifications were also carried out under various input voltageconditions. The proposed feedforward qPLL (FFqPLL) givesfast and accurate phase and frequency detection of the posi-tive sequence of the input signals, particularly in the start-upstage, with rapid input variation, and under unbalanced utilityconditions. The simplicity of the structure makes the presentedphase-finding system suitable for digital implementation.

II. CONVENTIONAL PLL SYSTEM

A PLL is a device that is able to keep an output signalsynchronized in frequency, as well as in phase, with a referenceinput signal. More precisely, the PLL is a servo system thatcontrols the phase of its output signal in order to minimizethe phase error between the output and reference phases. Atraditional PLL analysis system is based on a single inputsystem, as shown in Fig. 1. In the case of three-phase inputsignals, a small simplification is needed and the inputs can eas-ily be converted into a stationary αβ plane through the Clarketransformation or into a synchronously rotating reference framethrough the Park transformation. Starting from the αβ-planerepresentation of the three-phase input and adopting the spacevector representation proposed by Aredes in [23], the phaseerror signal can be expressed as

ud(t) = (u1αu2α + u1βu2β) + j(u1βu2α − u1αu2β). (1)

By applying Akagi’s instantaneous power theory [24], [25],two different approaches can be adopted to estimate the inputsignal phase angle. The first uses the real part of ud and yields apPLL system, while the second uses the real part of ud to yielda qPLL system.

The conceptual scheme of a classical qPLL system for autility interface is shown in Fig. 2, where ωd,n is the nominalline pulsation. Referring to the following symmetrical voltagesystem:

vabc = V [ sin θ sin(θ − 2π

3

)sin

(θ + 2π

3

)] (2)

where V and θ are the amplitude and the phase angle, respec-tively, Clarke’s transformation is characterized by the followingmatrix:

Tc =

√23

[1 −1/2 −1/20

√3/2 −

√3/2

](3)

which gives rise to the voltage system (vα, vβ)

vαβ =

√32· V · [ sin θ cos θ ] (4)

which represents the voltage system (2) in the αβ plane. Then,the algorithm in Fig. 2 can be used to calculate and regulate tozero the quantity

q(t) = vβiα − vαiβ = 3/2V sin(θ − θq) (5)

which is Akagi’s imaginary power associated both with thevoltage system (2) and the fictitious current system (iα, iβ).This represents a balanced current system with unitary ampli-tude and phase angle θq in the αβ plane.

Due to the action of the LF [typically proportional–integral(PI) controller], the algorithm in Fig. 2 may reach two equi-librium points under steady-state conditions. The former ischaracterized by

Δq = θ − θq = π (6)

and is unstable. In fact, if a slight positive phase variationoccurs, then Δq > π. For (5), q(t) becomes negative and theaction of the controller increases Δq. Likewise, if a slightnegative variation makes Δq < π, then the algorithm furtherreduces the value of Δq. The latter equilibrium point

Δq = 0 (7)

is stable. In fact, if a slightly positive phase variation occurs,making Δq > 0, for (5), q(t) becomes positive and the actionof the controller reduces Δq . Analogously, if a slight negativevariation makes Δq < 0, then the algorithm reduces the valueof Δq to zero.

The PI controller is used in conjunction with a feedforwardaction at the nominal pulsation ωd,n and is saturated in order toincrease the dynamic performance of the qPLL and avoid phaselocking on an eventual interharmonic component of the voltagesystem.

The conceptual scheme of a classical robust pPLL system fora utility has the same structure as that in Fig. 2. In addition, thisalgorithm relies on the transformation in (3), which is used toobtain the voltage system (vα, vβ) expressed by (4). Then, itcalculates and regulates to zero the p(t) value defined as

p(t) = vαiα + vβiβ = 3/2V cos(θ − θp) (8)

which is Akagi’s real power ([4]), which is associated withboth the voltage system (2) and the fictitious current system(iα, iβ) and represents a balanced current system with unitaryamplitude and phase angle θp in the αβ plane.

LICCARDO et al.: ROBUST AND FAST THREE-PHASE PLL TRACKING SYSTEM 223

Fig. 3. FFqPLL.

Moreover, it can be shown [20] that, due to the action of thecontroller, the algorithm may reach two equilibrium points. Theformer is characterized by

Δp = θd − θp = π/2 (9)

and is unstable. The latter, which is stable, is characterized by

Δp = θd − θp = −π/2. (10)

All of the results that are presented next are for a qPLLsystem, but are also applicable to a pPLL system.

A conventional PLL system implemented in an SRF uses a PIcontroller to track the phase angle of the grid voltages. The con-troller parameters represent a tradeoff between a fast dynamicsystem providing quick synchronization and a slow dynamicsystem providing an accurate filtered output. Therefore, underideal grid conditions, the conventional SRF-PLL gives goodresults. Under distorted and/or unbalanced supply voltages, thebandwidth of the PLL controller should be further reduced toprovide a good synchronization signal. However, reducing thePLL bandwidth results in an increase in response time, whichmeans that the system cannot track the phase angle (θ) quickly.

III. PROPOSED PHASE TRACKING SYSTEM

The proposed system is shown in Fig. 3. The idea is touse an open-loop synchronization method as a forward actionfor a modified classic qPLL. This tracking system has severaladvantages in terms of dynamics.

A. Input Signal Analysis

Referring to the following asymmetrical and distorted volt-age system, made of the sum of positive sequence and negativesequence distorted systems:

va =+∞∑k=1

[Vd,k sin(θd,k) + Vi,k sin(θi,k)]

vb =+∞∑k=1

[Vd,k sin

(θd,k − 2

3kπ

)+ Vi,k sin

(θi,k +

23kπ

)]

vc =+∞∑k=1

[Vd,k sin

(θd,k +

23kπ

)+ Vi,k sin

(θi,k − 2

3kπ

)]

(11)

where Vd,k and Vi,k are the amplitude of the kth harmonic com-ponent of the aforementioned positive and negative sequence

Fig. 4. Feedforward action.

systems and θd,k and θi,k are their phase angles, respectively. IfVd,k = 0 for k > 1 and Vi,k = 0 for any k, then (11) coincideswith (2). With this assumption, q(t) can be expressed as

q(t)=32

+∞∑k=1

Vd,k sin(θd,k − θd,q)+32

+∞∑k=1

Vi,k sin(θi,k − θd,q).

(12)

This equation can be divided into a dc component to becontrolled to zero and a disturbance component as follows:

q(t) = q(t) + q(t)

q(t) =32Vd,1 sin(θd,1 − θd,q)

q(t) =32

+∞∑k=2

Vd,k sin(θd,k − θd,q)

+32

+∞∑k=1

Vi,k sin(θi,k + θd,q). (13)

The disturbance component q(t) consists of the infinite sumof the sinusoidal signals at frequency multiples of the linefrequency, around the stable equilibrium point (7).

For any type of voltage system, it is possible to define thequantity q(t) and, thus, the lower disturbance frequency. Thisis useful information for the LF design. When the system isaffected by an interharmonic component, the situation is morecritical because q(t) may oscillate at a very low frequency.

B. Feedforward Action

The feedforward action shown in Fig. 4 guarantees the highdynamic performance of the phase locking in the start-up stage,as well as the low error in the steady state, in the presence ofasymmetrical and distorted supply voltage systems. Moreover,it is possible to estimate the frequency with high precision andfast dynamics. By taking into consideration the voltage system(2), whose representation in the αβ plane is expressed by (4),and applying a reference rotation synchronous with the nominalline frequency, the dq representation is obtained[

vd

vq

]=

[sin θn − cos θn

cos θn sin θn

] [vα

vβ

]

=

√32

⎡⎢⎢⎢⎣

cos(θd,1 − θn)︸︷︷︸=vd

− cos(θd,1 + θn)︸︷︷︸=−vd

sin(θd,1 − θn)︸︷︷︸=vq

+ sin(θd,1 + θn)︸︷︷︸=−vq

⎤⎥⎥⎥⎦ (14)

where θn = 2πfnt is the phase related to the nominal frequency(e.g., 50 Hz). The phase related to the real supply frequencyfd,1 is

θd,1 = 2πfd,1t + θ0d (15)


where θ0d is the initial phase of the positive sequence of the

supply voltage system (2). By low-pass filtering (14) and takinginto account that the lower frequency to eliminate is related tofd,1 + fn, the following quantities are obtained:

vd =

√32

cos(2π · Δf · t + θlpf + θ0

d

)=

√32

cos(θf )

vq =

√32

sin(2π · Δf · t + θlpf + θ0

d

)=

√32

sin(θf ) (16)

where Δf = fd,1 − fn and θlpf is the phase delay introducedby LPFf . By evaluating the arctangent of vq on vd, it ispossible to extract θf . If the supply voltage frequency and thenominal one are the same, Δf = 0, θlpf = 0, and the extractedvalue represents the initial phase. If Δf �= 0, this implies thatθlpf = 0 and a phase estimation error is obtained. In this case,the feedback action will compensate for the error. In any case,summing to θf , i.e., the nominal phase, θd,1 + θlpf is obtained.After deriving this quantity, the supply voltage frequency can beevaluated. The dynamic response and the steady-state precisionare strictly connected to the LPFf cutoff frequency chosen.

The bandwidth and the order of the LPFf must be deter-mined with reference to the voltage system (11), consideringthat the dq components present a disturbance component, as in

vd =32

+∞∑k=2

Vd,k cos(θd,k − θn)

− 32

+∞∑k=i

Vi,k cos(θi,k + θn) (17)

vq =32

+∞∑k=2

Vd,k sin(θd,k − θn)

+32

+∞∑k=i

Vi,k sin(θi,k + θn). (18)

Therefore, it must be taken into account that the lowerfrequency involved in (17) and (18) is equal to the line fre-quency and is due to the second-order harmonic of the negativesequence system. Even more critical is the situation connectedto the voltage system when affected by an interharmoniccomponent. In fact, vd and vq may oscillate at a very lowfrequency when the interharmonic component is located nearthe component at the line frequency.

C. Feedback Action

As mentioned before, if the supply frequency is not exactlyequal to its nominal value, vd and vq in (14) are not dcquantities. Therefore, during the low-pass filtering, they areaffected by the phase distortion of LPFf and θlpf �= 0. Hence,the resulting angle θf is not exactly equal to θd,1 and is affectedby a constant estimation error for a constant line frequencydifferent from fd,n. In order to reduce this residual estimationerror to zero, the use of the feedback action, based on theconventional PLL scheme shown in Fig. 3, is proposed. Dueto the aforementioned feedforward action, this last ensuresa tracking error equal to zero for a constant line frequencydifferent from fn.

Fig. 5. Linearized model of the FFqPLL.

In this case, the gain kp of the controller and the time constantτf of the LPF have to be determined while also taking intoaccount the influence of the residual voltage disturbance effectson the feedforward action on θd.

IV. LINEAR ANALYSIS AND DESIGN CRITERIA

This section discusses considerations about the design crite-ria of the proposed phase-locking system.

The FFqPLL can be modeled in the Laplace domain, asshown in Fig. 5. The feedforward transfer function G(s) de-pends only on the associated LPF LPFf . The poles of this filterare external to the feedback loop. Hence, the presence of thefeedforward action is not relevant in terms of stability. Thus, inthe following analysis, it will not be considered. However, thestability analysis is very similar to a conventional qPLL.

The qPLL and pPLL can be analyzed using the same ap-proach. For this reason, only the former will be considered inthis section. A small tracking error is hypothesized near theequilibrium point, i.e.,

θd,q∼= θd. (19)

It is worth noting that the pPLL also admits a linearizationmodel with the structure of the system in Fig. 5, near theequilibrium point

θd − θd,p∼= −π/2. (20)

Using the model in Fig. 5, it is possible to evaluate thetransfer functions describing the PLL behavior. The transferfunction considered for the first-order low-pass filter and thePI controller are reported in

PI = kp +ki

sLPF =

11 + sτf

. (21)

A. Stability

The system stability can be studied by evaluating transferfunction Θd,q, as shown in

Θd,q(s) = F1(s)Θd,1(s) + F2(s)Θn(s) + F3(s)Q(s) (22)

where

F1(s) =Vd,1(kps + ki)

s3τf + s2 + 32Vd,1kps + 3

2Vd,1ki

(23)

F2(s) =G(s)

s3τf + s2 + 32Vd,1kps + 3

2Vd,1ki

(24)

F3(s) =kps + ki

s3τf + s2 + 32Vd,1kps + 3

2Vd,1ki

. (25)


Fig. 6. Maximum ki value versus kp and LPF cutting frequency ft.

The system is stable if the characteristic polynomial (26)only has roots with negative real parts

p(s) = s3τf + s2 +32Vd,1kps +

32Vd,1ki. (26)

Using the Routh criteria, the stability is guaranteed if condi-tion (27) is verified

kp

ki> τf . (27)

The previous equation shows that the stability is dependenton the PI and LPF parameters. A fast graphical approach usefulfor designing the system is shown in Fig. 6. For the selected kp

and filter cutting frequency ft, the graph reports the maximumadmissible ki values for a stable system.

B. Error Estimation

The error dynamic can be analyzed by means of

E(s) = E1(s)Θd,1(s) + E2(s)Θn(s) + E3(s)Q(s) (28)

where

E1(s) =(1 + sτf )s2

s3τf + s2 + 32Vd,1kps + 3

2Vd,1ki

(29)

E2(s) =G(s)

s3τf + s2 + 32Vd,1kps + 3

2Vd,1ki

(30)

E3(s) = − kps + ki

s3τf + s2 + 32Vd,1kps + 3

2Vd,1ki

. (31)

Equation (28) can also be used to evaluate the steady-stateerror. By considering the feedforward input Θn(s) and thephase input Θd,1(s) as ramp inputs, the steady-state error isreported in

e∞(t) = e1 + e2 +n∑

i=1

Aqi |E3(jωqi)|

× sin (ωqit + θqi + Arg [E3(jωqi)]) (32)

TABLE IPLL PARAMETERS

where the presence of n generic disturbances have been consid-ered, as shown in

q(t) =n∑

i=1

Aqi sin(ωqit + θqi) (33)

according to the final value theorem

e1 = lims→0

sE1(s)ϑd,1

s2= 0 e2 = lim

s→0sE2(s)

Θn

s2≈ 0. (34)

In (34), e2 can be considered to be almost equal to zerobecause, when the gains of transfer functions (30) and (31) arecompared, the first one always presents a higher attenuation inthe disturbed frequency range.

It is clear from (32) and (34) that if the voltage is notcontaminated by disturbances such as harmonics or an un-balance, the steady-state error is zero. Otherwise, it dependson the disturbance entity according to (32). The designer canuse the aforementioned equations for the desired disturbanceattenuation and, thus, the desired steady-state error.

If the filtering of Q(s) is delegated to the PI controller as ina conventional PLL, an analysis can be made by evaluating allof the transfer functions with τf = 0. In this case, the systemis always stable and ki and kp have to be chosen accurately inorder to have an acceptable disturbance attenuation.

The presence of the filter leads to better results in termsof disturbance attenuation, such as unbalances. However, thesystem bandwidth is smaller, and therefore, the dynamic re-sponse is reduced. Adding the feedforward action enhances thedynamic response.

V. SIMULATION RESULTS

In this section, several simulation results are shown in orderto validate the analysis reported in the previous section and tocompare the conventional qPLL with the proposed topology.These numerical simulations were obtained from Simulinkmodels. The parameters used are reported in Table I.

A. Start-Up

As a first case, a noncontaminated direct sequence voltagecan be considered with amplitude Vd = 100 V. The consideredinitial phase values (ϕd) are π/8, π/4, and π/2.

The start-up stage will be considered in order to evaluate thephase locking. All of the results are shown in Figs. 7–9. Theseshow that, as stated in Section I, the steady-state error is zero inthe case of a nondistorted voltage.

In all of the simulation results, it is possible to observe thatthe FFqPLL error is always smaller than the classical qPLL,independently from the initial phase. This means that, duringthe start-up stage, the synchronization error is reduced, leadingto a higher power factor.


Fig. 7. ϕd = π/8. (1) Phase error. (2) qPLL output. (3) FFqPLL output.

Fig. 8. ϕd = π/4 phase error.

Fig. 9. ϕd = π/2 phase error.

In order to test the start-up stage even when a disturbance ispresent, simulations were carried out in the case of a nonidealsupply. The results shown in Fig. 10(a)(1) show the start-upphase error in the case of a nonideal supply frequency of48 Hz. Moreover, in Fig. 10(b)(1) and (c)(1), the presenceof a 30% unbalance and 1-Hz subharmonic is considered.The respective locked frequencies are shown in Fig. 10(a)(2),10(b)(2), and 10(c)(2). The simulation results show that, evenin the case of nonideal voltages, the FFqPLL presents a smallererror in the start-up period.

B. Disturbed Voltage

In order to evaluate the performance of the PLL in a dis-torted network, a disturbed voltage is considered in the nextsimulations.

1) Unbalance: The presence of a 30% unbalance can beanalyzed considering Vd = 100 V and Vi = 30 V. The initialphases considered in the simulations are ϕd = 0 and ϕI = 0.In order to evaluate the benefits of the proposed method, theparameters reported in Table I have been chosen to give thesame system dynamics.


Fig. 10. Start-up in nonideal conditions.

Fig. 11. Error E3(s) bode diagram.

The E3(s) bode diagram is shown in Fig. 11 to evaluate thesteady-state error. In this case, the disturbance is

q(t) =3230 sin(2π100t + ϕd + ϕi). (35)

The amplitude attenuation is |E3(j2π100)|dB = −78; there-fore, the resultant steady-state error amplitude is 0.0057 rad.

The disturbance is introduced at 1 s. Fig. 12(1) shows theerror dynamics, with an enlargement shown in Fig. 12(2). Inthe latter figure, only the effect of E3(s) is appreciable, whilethe error due to E2(s) is negligible, as shown in Section IV.

Fig. 12. 30% unbalance–phase error. (1) Phase error. (2) Phase-errorenlargement.

It is possible to observe that the FFqPLL and the conventionalPLL have the same dynamics, but the former presents a higherattenuation as expected.


Fig. 13. Phase error for 10% fifth and 5% eleventh harmonics. ϕd = 0, ϕi,5 = 0, and ϕi,11 = 0.

Fig. 14. Phase error for 10% subharmonic.

Fig. 15. Supply frequency variation.

2) Harmonics: The presence of harmonics can also be con-sidered in this section. A 10% fifth harmonic and a 5% eleventhharmonic are added to the fundamental at 1 s. The PLLs’parameters are the same as those in the case of unbalance.

The results are shown in Fig. 13.3) Subharmonics: The performances of the PLLs in the

presence of 10% subharmonic oscillations at a very low fre-quency (1 Hz) are illustrated in this case. Fig. 14 shows thesimulation results.

4) Supply Frequency Variation: To test the performance ofthe proposed PLL during supply frequency variation, a 2-Hzdrop of 2-s duration was given at 0.4 s. The settling time wasfound to be about 120 ms (Fig. 15).

In all of the aforementioned simulations, the conventionalqPLL and the FFqPLL successfully locked the desired phaseeven under distorted conditions. Comparing the two systems,the FFqPLL has shown improved performance, owing to thebenefits of the error filtering and the feedforward action. In fact,the presence of the feedforward action enhances the systemdynamics, which are reduced by the LPF needed to have a smallsteady-state error.

Compared with the new PLL topologies, such as ANF basedor EPLL, the proposed technique seems to show comparable

TABLE IIPLL PARAMETERS

results in terms of dynamics and steady-state error. However,FFqPLL presents higher dynamics in the start-up stage underall nonideal supply conditions. Moreover, the simplicity ofFFqPLL makes this an interesting technique for both analogand digital implementations.

Finally, the simulation results confirm the linear analysismade in Section IV.

VI. EXPERIMENTAL RESULTS

In this section, several experimental results are presented.The qPLL and the FFqPLL were implemented with fixed-pointarithmetic in a TMS320F240 DSP using an analog-to-digitalconverter at a 10-kHz sampling frequency. A controlled powersource was employed to generate the desired input voltage. Theparameters used are reported in Table II.


Fig. 16. Nondistorted input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.

Fig. 17. 12.5% unbalanced input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.

In order to compare the experimental and simulation results,the same conditions as those in the previous section were con-sidered for the input voltage. The results shown in Figs. 16–19show that the experimental results match the numerical ones.Each figure shows that the PLL outputs overlapped with thereference phase voltage and that the evaluated PLL error iscomparable with that of the simulation.

VII. CONCLUSION

In this paper, a robust and fast three-phase tracking sys-tem has been shown. The proposed PLL structure for theestimation of the phase angle of the fundamental positive

sequence of the supply voltage system consists of feedfor-ward and feedback actions. This PLL, compared with theclassical qPLL and pPLL structures, improves the dynamicand steady-state estimation performances. The start-up stageis very fast in any utility condition, and the performancesin unbalanced conditions are better than conventional PLLsystems and are comparable with the most recent algorithmsproposed in the literature. Moreover, the proposed methodtracks the frequency variations well. A steady-state error analy-sis in the Laplace domain was performed to define the designcriteria.

Simulation and experimental results were compared andshowed good agreement.


Fig. 18. 10% fifth and 5% eleventh harmonics in input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.

Fig. 19. 10% subharmonics at 1 Hz in input voltage. (1) qPLL output. (2) FFqPLL output. (3) qPLL phase error. (4) qPLL phase error.

The proposed PLL can be employed in any supply voltagecondition in order to lock the positive sequence component,and the simplicity of this structure makes the presented phase-locking system suitable for digital implementation.

REFERENCES

[1] G. C. Paap, “Symmetrical components in the time domain and their appli-cation to power network calculations,” IEEE Trans. Power Syst., vol. 15,no. 2, pp. 522–528, May 2000.

[2] B. Singh, K. Al-Haddad, and A. Chandra, “A review of active filters forpower quality improvement,” IEEE Trans. Ind. Electron., vol. 46, no. 5,pp. 960–971, Oct. 2001.

[3] G. Bonifacio, A. Lo Schiavo, P. Marino, and A. Testa, “A new highperformance shunt active filter based on digital control,” in Proc. IEEEPES Winter Meeting, 2000, vol. 4, pp. 2961–2966.

[4] S.-K. Chung, “A phase tracking system for three phase utility interfaceinverters,” IEEE Trans. Power Electron., vol. 15, no. 3, pp. 431–438,May 2000.

[5] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, “Overviewof control and grid synchronization for distributed power generationsystems,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1394–1409,Oct. 2006.

[6] F. Liccardo, P. Marino, and M. Trigianese, “An efficient connection be-tween grid and wind farm by means an Synchronous AFE,” in Proc.SPEEDAM Symp., Taormina, Italy, 2006, pp. 1211–1216.

[7] M. Karimi-Ghartemani and M. R. Iravani, “A method for synchroniza-tion of power electronic converters in polluted and variable-frequencyenvironments,” IEEE Trans. Power Syst., vol. 19, no. 3, pp. 1263–1270,Aug. 2004.

[8] R. M. Santos Filho, P. F. Seixas, P. C. Cortizo, L. A. B. Torres, andA. F. Souza, “Comparison of three single-phase PLL algorithms for UPSapplications,” IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 2923–2932,Aug. 2008.


[9] M. A. Perez, J. R. Espinoza, L. A. Moran, M. A. Torres, and E. A. Araya,“A robust phase-locked loop algorithm to synchronize static-power con-verters with polluted AC systems,” IEEE Trans. Ind. Electron., vol. 55,no. 5, pp. 2185–2192, May 2008.

[10] A. M. Salamah, S. J. Finney, and B. W. Williams, “Three-phase phase-lock loop for distorted utilities,” IET Electr. Power Appl., vol. 1, no. 6,pp. 937–945, Nov. 2007.

[11] V. Kaura and V. Blasko, “Operation of a phase locked loop system underdistorted utility conditions,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 58–63, Jan./Feb. 1997.

[12] A. V. Timbus, M. Liserre, F. Blaabjerg, R. Teodorescu, and P. Rodriguez,“PLL algorithm for power generation systems robust to grid faults,” inProc. IEEE Power Electron. Spec. Conf., 2006, pp. 1360–1366.

[13] J. M. Espi Huerta, J. Castello, J. R. Fischer, and R. Garcia-Gil, “A syn-chronous reference frame robust predictive current control for three-phasegrid-connected invert,” IEEE Trans. Ind. Electron., vol. 57, no. 3, pp. 954–962, Mar. 2010.

[14] H. Song and K. Nam, “Instantaneous phase-angle estimation algo-rithm under unbalanced voltage-sag conditions,” Proc. Inst. Elect. Eng.,vol. 147, no. 6, pp. 409–415, Nov. 2000.

[15] D. Yazdani, A. Bakhshai, G. Joos, and M. Mojiri, “A nonlinear adaptivesynchronization technique for grid-connected distributed energy sources,”IEEE Trans. Power Electron., vol. 23, no. 4, pp. 2181–2186, Jul. 2008.

[16] D. Yazdani, M. Mojiri, A. Bakhshai, and G. Joos, “A fast and accuratesynchronization technique for extraction of symmetrical components,”IEEE Trans. Power Electron., vol. 24, no. 3, pp. 674–684, Mar. 2009.

[17] D. Jovcic, “Phase locked loop system for FACTS,” IEEE Trans. PowerSyst., vol. 18, no. 3, pp. 1116–1124, Aug. 2003.

[18] S. Shinnaka, “A robust single-phase PLL system with stable andfast tracking,” IEEE Trans. Ind. Appl., vol. 44, no. 2, pp. 624–633,Mar./Apr. 2008.

[19] P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, andD. Boroyevich, “Decoupled double synchronous reference frame PLL forpower converters control,” IEEE Trans. Power Electron., vol. 22, no. 2,pp. 584–592, Mar. 2007.

[20] G.-C. Hsieh and J. C. Hung, “Phase-locked loop techniques. A survey,”IEEE Trans. Ind. Electron., vol. 43, no. 6, pp. 609–615, Dec. 1996.

[21] M. Karimi-Ghartemani and M. R. Iravani, “A new phase-locked loop(PLL) system,” in Proc. 44th IEEE MWSCAS, 2001, vol. 2, pp. 421–424.

[22] D. R. Costa, L. G. B. Rolim, and M. Aredes, “Analysis and softwareimplementation of a robust synchronism circuit-PLL circuit,” in Proc.IEEE Int. Symp. Ind. Electron., 2003, vol. 1, pp. 292–297.

[23] L. G. B. Rolim, D. R. da Costa, and M. Aredes, “Analysis and soft-ware implementation of a robust synchronizing PLL circuit based on thepq theory,” IEEE Trans. Ind. Electron., vol. 53, no. 6, pp. 1919–1926,Dec. 2006.

[24] H. Akagi, Y. Kanazawa, and A. Nabae, “Generalized theory of the in-stantaneous reactive power in three-phase circuits,” in Proc. IPEC, 1983,pp. 1375–1386.

[25] H. Akagi, Y. Kanazawa, and A. Nabae, “Instantaneous reactive powercompensator comprising switching devices without energy storage com-ponents,” IEEE Trans. Ind. Appl., vol. IA-20, no. 3, pp. 625–630,May/Jun. 1984.

[26] F. Liccardo, P. Marino, C. Schiano, and N. Visciano, “A new robustphase tracking system for asymmetrical and distorted three phase net-works,” in Proc. 11th Int. Conf. Harmon. Quality Power, Sep. 12–15,2004, pp. 525–530.

Felice Liccardo was born in Naples, Italy, on May 8,1975. He received the M.Sc. degree in computerscience engineering from the University of Naples“Federico II,” Naples, in 2001 and the Ph.D. degreein electrical energy conversion from the Second Uni-versity of Naples, Aversa, Italy, in 2005.

He is currently with the Second University ofNaples. His research interests include power elec-tronic converters for power quality improvement.

Pompeo Marino was born in Frosinone, Italy, onApril 8, 1948. He received the M.Sc. degree in elec-tronics engineering from the University of Naples“Federico II,” Naples, Italy, in 1973.

He is a Professor in industrial electronics andelectrical drives with the Dipartimento di Ingegne-ria dell’Informazione, Second University of Naples,Aversa, Italy. He is engaged in research works onelectrical power system reliability and harmonicanalysis. His interests include power converter de-sign, ac and dc drives, and motion control.

Giuliano Raimondo was born in Naples, Italy, onJanuary 23, 1983. He received the B.Sc. and M.Sc.degrees in electronics engineering from the SecondUniversity of Naples, Aversa, Italy, in 2005 and2008, respectively, where he is currently working to-ward the Ph.D. degree and in the Laboratoire Plasmaet Conversion d’Energie, University of Toulouse,Toulouse, France.

His research interests include digital control andpower electronic converters for power quality im-provement in railway networks.

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