04159478

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 4, NOV. 1979

Design Considerations in Class D MOS

Power Amplifiers

JOHN M. MURRAY, MEMBER, IEEE, AND GERALD M. OLESZEK, SENIOR MEMBER, IEEE

Abstract-The theory and design of high-efficiency Class D (SwitchingMode) power amplifiers incorporating MOS power transistors are con-sidered in this paper. Class D amplifiers suitable for servo, audio, andgeneral purpose industrial applications are presented. Feedback tech-niques in Class D amplifiers are also examined.

I. INTRODUCTIONCLASS D POWER amplifers [1] have received renewed_attention with the introduction of MOS power field-

effect transistors [2]-[4]. Efficiencies exceeding 85 percenthave been achieved in Class D amplifiers implemented withMOS power devices. The unique characteristics of MOS powertransistors, including switching delay times ranging from5-100-ns and 0.2-4-Q on-state resistance values, have allowedthese efficiency levels to be attained. The theory and imple-mentation of Class D power amplifiers incorporating MOSpower transistors will be considered in this paper.A generalized Class D MOS power amplifier is illustrated in

Fig. 1. The amplifier input signal is applied to a pulsewidthmodulator operating at a fixed carrier frequency f,. Themodulator output pulsewidth is proportional to the instan-taneous value of the input signal. A driver stage following themodulator provides the level translation capability requiredto drive the MOS power output stage. The power output stageproduces a high-level version of the original pulsewidth modu-lated waveform. The filter following the power output stagepasses only those signal components proportional to theoriginal input waveform. As a result of the filtering process,an amplified version of the original input waveform appearsacross the load.

Il. THEORY

The MOS power input stage waveform may be representedanalytically [5] as follows:

VOUT =F( (t) + F((t) 1)

where

M c mco tF,(t) k + 2COScosniod t + E isin

JS

(MT s(m co, t - 2imnk)rn=i MIn

Manuscript received May 19, 1979; revised July 22, 1979.The authors are with the Department of Electrical Engineering, Uni-

versity of Colorado, Colorado Springs, CO 80907.

o m=+ J,(mrrM) (rn=i n± i Sinfl\ct + ncmod t

- 2mnk-n-cmod)2

F2 (t) = F1 (- t)

and

ci

Xmod

k

(2)

(3)

= carrier frequency.= modulation frequency,= modulation index,= the ratio, in the absence of modulation, of the pulse

duration to the interval between pulse centers.

It can be seen from the above expressions that the outputsignal consists of a dc term, a term proportional to the inputor modulation signal, harmonics of the carrier frequency,and sidebands about the carrier and its harmonics. The side-bands may be seen to be integral multiples of the modulationfrequency. The output signal component proportional to themodulation signal, i.e., the desired output signal, may beextracted from (1) by filtering. The filter should be designedsuch that the dc term, the carrier, and associated harmonicsand sidebands are significantly attenuated without reducingthe amplitude of the desired signal component. If we assumethat the dc term has been removed by high-pass filtering orappropriate level shifting, a low-pass filter may be used toeliminate the high-frequency terms.The spectrum of the power output stage waveform from an

experimental Class D MOS power is illustrated in Fig. 2. Thespectral components can be shown to correspond with thosepredicted by (1). It can be seen that the carrier signal andsidebands located at fc - 2fmod and f. + 2fmod dominate thehigh-frequency portion of the spectrum. A second-order low-pass filter having a cutoff frequency equal to the maximummodulation frequency was utilized to attenuate the carrierand associated sidebands. An attenuation figure of 40 dB atf =f = lOfmoj was realized for this case. Additional outputripple reduction may be obtained by utilizing higher orderlow-pass filters or by increasing the separation between themaximum modulation frequency and the carrier frequency.

III. IMPLEMENTATIONThe most critical factor in the implementation of a Class D

power amplifier is the design of the output stage. MOS poweroutput stages capable of meeting a variety of system require-

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211

212 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 4, NOV. 1979

INPUT OUTPUT

LOAD

Fig. 1. Generalized Class D MOS power amplifier.

ments are illustrated in Fig. 3. The operational characteristicsof each of these output stages will be examined in this section.In addition, feedback in Class D amplifiers will be considered.

A. Output Stage DesignThe Class D output stage illustrated in Fig. 3(a) operates

from a single power supply and is ac coupled to the load viacapacitor C3. A pulsewidth modulated input signal is appliedto the gate of output transistor Q4 and the base of drivertransistor Q,1. The input signal is inverted by Ql, yielding acomplimentary drive signal at the gate of output transistorQ3. During operation, a high-level input to the stage causesQ4 to conduct, forcing the output to approach ground poten-tial. The corresponding low-level signal developed at the gateof Q3 forces the device into the nonconducting or "off" state.Conversely, a low-level input to the stage produces a high-levelsignal at the gate of Q3, forcing the device to enter the con-ducting or "on" state. Assuming the on-state resistance of Q3is significantly less than the load seen by the stage, the outputvoltage approaches the positive supply level. Output transistorQ4 is forced into the "off" state while Q3 is conducting due tothe low-level signal present at its gate. The bootstrappedemitter follower consisting of Q2, R2, C2, DI, and D2 pro-vides the high-level signal required to properly drive transistorQ3- The amplitude of the drive signal generated by the emit-ter follower may be calculated as follows:

Vc2 (Q4 conducting) = V - VD, - VONQ. (4)

VE2 (Q3 conducting) = VOUT + VC2 -VBE2 (5)

VOUT(Q3 conducting) = V- VONQ3 (6)where

V = power supply voltageVONQ = output voltage with Q4 "on", Q3 "off"

VONQ = V-output voltage with Q3 "on", Q4 "off".

Therefore,

VD, =VE2 2 V VD, VBE2 VONQ VON¢,

The drive signal must satisfy the following conditions:

VID0e > VOUT(Q3 conducting) + VGSMIN

VDHjye - VOUT(Q3 conducting)<BVGS(Q3)

_ ~~~~~~~~~~~~~A

I ;~~~~~~~~~~~~~~5

fc 2fmod fcfcc +2fmod

fc 200KHz fmod 5 20KHz

Horizontal Scale: 20KHz/Div.

Fig. 2. Class D amplifier output spectrum.

where

VGSMIN = gate-to-source voltage required to produce thedesired load current

BVGS (Q3) = gate-to-source breakdown voltage (Q3).

Assumning the MOS device model parameters are known, ananalytical solution [61 for VGSMIN may be obtained by solv-ing the MOS device ohmic region equation and the load lineequation simultaneously. An alternate approach utilizingpublished -or measured device characteristics in conjunctionwith load line specifications yields the same result. In additionto providing the necessary drive level, the emitter followerrapidly charges the gate capacitance of output transistor Q3.The gate capacitance of Q3 is discharged via D2 when Q, tumson. Resistors R3 and R4 limit the peak current supplied byQ2 and the input driving source, respectively. It should benoted that driver transistor Q, and emnitter follower transistorQ2 must be capable of sustaining collector to emitter voltagesof approximately 2 V. This factor tends to limit the applica-bility of bipolar transistors in Class D amplifiers since it isdifficult to obtain high voltage bipolar transistors capable ofswitching several amperes in the nanosecond time frame re-quired for high-efficiency Class D operation. The drive levelrequirements for output transistor Q4 may be determineddirectly from device characteristic data and the application ofthe load line equation.

+V r rI I I

I j _T_=171 IrT J, I I.I L _1 L

MURRAY AND OLEZEK: DESIGN CONSIDERATIONS IN CLASS D POWER AMPLIFIERS

v.in

(a)

Rload

(b)

(c)

Fig. 3. (a) AC-coupled output stage-bipolar driver. (b) AC-coupled output stage-MOS driver. (c)DC-coupled output stage-bipolar driver. (d) DC-coupled output stage-MOS driver. (e) Bridge out-put stage.

R1 oad

vin

213

vin


(d)

(e)

Fig. 3. (Continued.)

The Schottky barrier diodes connected across the outputtransistors serve two purposes. Both devices limit inductivetransients which occur during the switching process. In addi-tion, diode D3 provides a mechanism for sinking current whichwould otherwise flow into the source of the upper MOS out-put transistor [7]. Fast recovery rectifiers may be utilizedalternately in high voltage applications.The frequency response of the amplifier is determined by

the output filter response characteristic at the high end of thespectrum and by the coupling capacitor-load resistor timeconstant at the low end of the spectrum. Adequate decou-pling of the power supply in the immediate vicinity of the out-put stage is necessary in order to assure proper frequency re-

sponse characteristics and to minimize switching transients on

the power supply line.The power delivered to the load from the output stage of

Fig. 3(a) may be determined from the equivalent circuit ofFig. 4. The overall system efficiency may also be calculatedusing the equations provided in Fig. 4.An experimental Class D amplifier is illustrated in Fig. 5. It

can be seen from Table I that a close correspondence existsbetween the theoretical and experimental amplifier perfor-mance characteristics. The efficiency of the amplifier may be

improved by paralleling output transistors in order to achievelower effective on-state resistance, by operating the outputstage at higher power levels, or by introducing a delay equali-zation network in the circuit to minimize power dissipationduring switching.

It is worthwhile to examine the factors contributing topower dissipation during switching. The process of chargingand discharging the internal MOS device capacitances requiresa finite energy expenditure on the part of the driving source.A substantially greater energy expenditure results when theoutput transistors conduct simultaneously during switchingdue to switching time delay variations in the MOS devices.Additional delay introduced by the inverting driver stage alsocontributes to the problem. The net result of this activity isto reduce the overall system efficiency. In the experimentalamplifier of Fig. 5, a I-percent loss in system efficiency maybe attributed to this effect. A delay network which may beused to eliminate this problem is illustrated in Fig. 6. Theswitching times of the output power transistors may be ad-justed via RA such that it is impossible for both output devicesto conduct simultaneously.The ability of the output stage of Fig. 5 to supply power

to a given load is limited primarily by the breakdown voltage

Yin

+V1

R3 V

1V

V.in

VI oad

Rioad

) Vin


Ron (MOS)

Vload(RMS)2 1 Y+ RL 2

load =RL RL 2(2)k R +Rn+R n

Rind V loadtotal =pulse-width + driver + load + MOS ind +switching

modulator

>L poutput stage

ploadSnystem Efficiency=

'totalR (MOS)

Fig. 4. Output stage equivalent circuit.

Fig. 5. Class D MOS power amplifier.

215

-


O-VW-O--v

I

J I I

ONI

I I ,, ,.

OFF I ON

ON OFF

Fig. 6. Delay network.

of the high speed bipolar driver transistors. An alternativehigh voltage output stage incorporating an MOS driver transis-tor is illustrated in Fig. 3(b). The load seen by the MOS drivertransistor consists of a current limiting resistor, Rx in serieswith an inductor Lx. The gate capacitance of Q2 may be seen

to be in parallel with this network. Circuit operation is as

follows: Assume Q, has been conducting for some time and a

current equal to + VIRx flows through Lx. When Q, turns off,the current through Lx will continue to flow, rapidly chargingthe gate-to-source capacitance of output transistor Q2. It isnecessary to select Rx, Lx in such a manner that the gate tosource voltage of Q2 reaches the desired drive level in therequired switching time interval. Zener diode DI protects thegate of Q2 from excessive gate-source voltage excursions whileD2 assures that no steady state current will flow from theoutput node through DI to ground. The high breakdownvoltage ratings of available MOS power transistors (80-400V) make this output stage design attractive when high outputpower levels are desired.

TABLE ICLASS D AMPLIFIER PERFORMANCE

Parameters Theoretical Performance Measured Performance(Assuming Ron = .-2Q)

PLoad 6.752W 6.245W

pOutput Stage 7.420W 6.913W

PTota1 7.638W 7.131W

'iOutput Stage 91.00% 90.34%

System 88.40% 87.58%

A dc coupled Class D amplifier power output stage is illus-trated in Fig. 3(c). The circuit operates from bipolar powersupplies and employs p-n-p switching transistors to performthe level shifting function necessary to provide appropriatedrive levels for the output transistors. A high-voltage imple-mentation of the dc-coupled output stage is shown in Fig.3(d). The high-voltage implementation utilizes an MOS power

+V

TO GATE Q4

+V

TO BASE Q1

Base Q1

Gate Q3

Gate Q4


SUMMING AMPLIFIER PULSE WIDTH MODULATOR

CLOSED LOOP GAIN = Vload = -G

Vin. + GH

Kw,_ (RA/R8)w'O2Where: G =

s + w 2 2

L iL+ 2~w oS I+w

RB

Kc

KloadK= =5.6Vx

Wi = 2; x 50KHz w0 = 2; x 20KHz

C = .866

ICLOSED LOOP GAIN[ = 2.57 = 8.2dB

T.H.D. < 1% IKHz

Fig. 7. Feedback amplifier.

transistor in the driver stage and an operational amplifier-basedcontrolled current source to provide the necessary level shift-ing function. Current source level shifting eliminates the prob-lem of obtaining high voltage, high-speed p-n-p switchingtransistor for the driver stage. In the circuit of Fig. 3(d), thep-n-p transistors must only satisfy the breakdown voltagerequirements associated with the level translation process.The power output stage illustrated in Fig. 3(e) utilizes four

MOS transistors in a bridge configuration to obtain a fourfoldincrease in power output over that obtainable from the circuitof Fig. 3(a). It should be noted that the bridge configurationrequires the load to float with respect to ground.

B. FeedbackFeedback in Class D amplifiers serves to stabilize the closed

loop amplifier gain against parametric variations in the systemcomponents and reduces distortion due to nonlinearities inthe pulsewidth modulator. A Class D amplifier incorporatingfeedback is illustrated in Fig. 7. The loop gain (GH) of theamplifier may be seen to be equal to the product of the gainof the open-loop Class D amplifier stage (K) and the resistorratio RAIRC. The complex conjugate pole pair associatedwith the second order filter and the single pole contributed bythe summing amplifier constitute the open loop poles of thesystem. It can be shown that instability will result if the loop

Vin

217


gain exceeds 15 dB. It should be noted that phase-lead com-pensation may be utilized in the amplifier of Fig. 7 to achievegreater phase margin and improved transient response.

IV. CONCLUSIONSThe theoretical and practical aspects of high efficiency Class

D MOS power amplifier have been considered in this paper.Logical extensions to this work include the development ofappropriate shielding techniques for the suppression of radiofrequency interference produced as a result of Class D opera-tion, the generation of analytical expressions describing ClassD amplifier distortion, and the improvement of Class Damplifier efficiency through the use of transformer coupling.

REFERENCES

[11 K. K. Clarke and D. T. Hess, Communication Circuit s: Analysisand Design. Reading, MA: Addison-Wesley, 1971, pp. 426-432.

[21 C. A. T. Salama and J. G. Oakes, "Nonpianar power field-effecttransistors," IEEE Trans. Electron. Dev., vol. ED-25, Oct. 1978.

[3] K. P. Lisiak and J. Berger, "Optimization of nonplanar powerMOS transistors," IEEE Trans. Electron. Dev., vol. ED-25, Oct.1978.

[4] Siliconix Inc., VMOS Power FETDesign Catalog, Mar. 1979.[51 H. S. Black, Modulation Theory. Princeton, NJ: Van Nostrand,

1953, pp. 275-276.[61 A. S. Grove, Physics and Technology of Semiconductor Devices.

NY: Wiley, 1967, 323.[71 K. K. Clarke and D. T. Hess, Communication Circuits: Analysis

and Design. Reading, MA: Addison-Wesley, 1971, pp. 426-432.

Pulsewidth Modulated DC Control: AParameter Variation Study with Current

Loop Analysis

CHARLES K. TAFT, MEMBER, IEEE, AND EDWIN V. SLATE

Absttuct-Pulsewidth modulated amplifiers have been shown to offermany advantages over proportional amplifiers when used to drive dcmotors. This paper is written in an attempt to better understand andutilize the benefits offered by pulsewidth modulation.The basic principles and characteristics of pulsewidth modulated

amplifiers were reviewed first. After presenting simplified models ofthe amplifiers, the current wavefonn in the steady state will be analyzed,and the effect of motor inductance determined.The effects of closing a current loop around the amplifier will be con-

sidered. Factors such as closed-loop dynamics and short-circuit protec-tion will be discussed.

1. INTRODUCTIONPULSEWIDTH modulated amplifiers have been shown to

offer considerable advantages in the control of dc motors.In the actual use of pulsewidth modulated amplifiers there areseveral points which must be clearly understood before the fullpotential of the amplifiers may be utilized.This paper will first review the basic principles and character-

istics of pulsewidth modulated amplifiers. After presentingsimplified models of the amplifiers, the differential equationsdescribing each amplifier-motor system (unidirectional and

Manuscript received September 12, 1978; revised July 22, 1979.The authors are with the University of New Hampshire, Durham,

NH 03824.

bidirectional) will be written. This mathematical descriptionprovides a means of analyzing the current waveform in thesteady-state due to an inductive load (such as a dc motor). Theeffects of parameter variation on steady-state current will bestudied with an emphasis on the role and effects of the seriesinductor. The remainder of the paper will be spent in discuss-ing the benefits of closing an inner current loop around thepulsewidth modulated amplifier.

II. A REVIEW OF THE PRINCIPLES OF PULSEWIDTHMODULATED AMPLIFIERS

1) Pulsewidth modulated amplifiers are amplifiers that utilizetransistors operating in the switching mode. By switching thetransistors on and off into saturation, power losses in the tran-sistor junctions are minimized. This means a cost savings tothe designer in terms of less expensive power transistors andreduced heat sinking.2) If the power transistors are switched between two volt-

age levels, at a frequency well beyond the driven system band-width, the motor will filter the high-frequency componentsof the modulated signal and respond to the low-frequencycomponents or dc level of the signal.3) There are basically two methods of obtaining a pulse-

width modulated signal.

0018-9421/79/1 100-0218$00.75 © 1979 IEEE

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04159478