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8/13/2019 [03] Chapter02_Logic Design With MOSFETs
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Introduction to VLSI Circuits and Systems, NCUT 2007
Chapter 02Logic Design with MOSFETs
Introduction to VLSI Circuits and Systems
Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007
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Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS Transmission Gate Circuits
Clocking and Dataflow Control
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nMOS Transistor
Four terminals: gate (G), source (S), drain (D), body (B)
Gateoxidebody stack looks like a capacitor
Gate and body are conductors
SiO2(oxide) is a very good insulator
Called metaloxidesemiconductor (MOS) capacitor
Even though gate is no longer made of metal
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nMOS Operation (1/2)
Body is usually tied to ground (0 V)
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
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nMOS Operation (2/2)
When the gate is at a high voltage
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain,
transistor is ON
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pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
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Ideal Switches (1/3)
CMOS integrated circuits use bi-directional devices called MOSFETs as
logic switches
Controlled switches, e.g, assert-high and assert-low switches
An assert-high switch is showing in Figure 2.1
Figure 2.1 Behavior of an assert-high switch
(a) Open (b) Closed
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Ideal Switches (2/3)
g = (a1)b = (a1)b
g = (a1) + (b1) = a + b
Figure 2.2 Series-connected switches
Figure 2.4 Parallel-connected switches
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Ideal Switches (3/3)
Figure 2.5 An assert-low switch
(a) Closed
(b) Open
Figure 2.6 Series-connected complementary switches
Figure 2.7 An assert-low switchFigure 2.8 A MUX-based
NOT gate
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Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS Transmission Gate Circuits
Clocking and Dataflow Control
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MOSFET as Switches
Early generations of silicon MOS logic
circuits used both positive and negative
supply voltagesas Figure 2.10 showing
In modern designs require only a single
positive voltage VDD and the groundconnection, e.g. VDD= 5 V and 3.3 V or
lower
The relationship between logic variables
xand itsvoltages Vx
Figure 2.11 Single voltage power supply
Figure 2.10 Dual power supply voltages
(a) Power supply connection (b) Logic definitions
DDx VV 0
VVthatmeansx x 00
DDx VVthatmeansx 1
(2.14)
(2.15)
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Switching Characteristics of MOSFET
In general,
The transition region between the highest
logic 0 voltage and the lowest logic 1
voltage is undefined
nFET
pFET
Figure 2.13 pFET switching characteristics
(a) Open (b) Closed
Figure 2.12 nFET switching characteristics
(a) Open (b) Closed
Low voltages correspond to logic 0 values High voltages correspond to logic 1 values
1 AiffvalidiswhichAxy
0 AiffvalidiswhichAxy
(2.16)
(2.17)
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nMOS FET Threshold Voltages
An nFET is characterized by a threshold voltage
VTnthat is positive, typical is around VTn= 0.5 V
to 0.7 V
If , then the transistor acts like an open
(off) circuit and there is no current flow betweenthe drain and source
If , then the nFET drain and source are
connected and the equivalent switch is closed (on)
Thus, to define the voltage VA that is associated
with the binary variableA
Figure 2.14 Threshold voltage of an nFET
(a) Gate-source voltage
(b) Logic translation
TnGSn VV
TnGSn VV
GSnA VV (2.20)
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pMOS FET Threshold Voltages
Figure 2.15 pFET threshold voltage
(a) Source-gate voltage
(b) Logic translation
An pFET is characterized by a threshold voltage
VTpthat is negative, typical is around VTp=0.5
V to0.8 V
If , then the transistor acts like an open (off)
switch and there is no current flow between the drain
and source
If , then the pFET drain and source are
connected and the equivalent switch is closed (on)
Thus, to the applied voltage VA we first sum
voltage to write
TpSGp VV
TpSGp VV
DDSGpA VVV VVA 0
DDA VV SGpDDA VVV
(2.23)
(2.24)(2.26)
TpDD VV (2.25)
Note that the transition between alogic 0 and a logic 1 is at (2.25) !
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nFET Pass Characteristics
An ideal electrical switch can pass any voltage
applied to it
As Figure 2.16(b), the output voltage Vy is
reduced to a value
Which is less than the input voltage VDD, called
threshold voltage loss
Thus, we say that the nFET can only pass a weaklogic 1; in other word, the nFET is said to pass a
stronglogic 0can pass a voltage in the range
[0, V1]
Figure 2.16 nFET pass characteristics
(a) Logic 0 transfer
(b) Logic 1 transfer
TnDD VVV 1 since TnGSn VV (2.27)
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pFET Pass Characteristics
Figure 2.17(a) portrays the case where Vx=
VDD corresponding to a logic 1 input. The
output voltage is
Figure 2.17(b), the transmitted voltage canonly drop to a minimum value of
The results of the above discussion
nFETs pass strong logic 0 voltages, but weaklogic 1 values
pFETs pass strong logic 1 voltages, but weak
logic 0 levels
Use pFETs to pass logic 1 voltages of VDD
Use nFETs to pass logic 0 voltages of VSS= 0 V Figure 2.17 pFET pass characteristics
(a) Logic 0 transfer
(b) Logic 1 transfer
DDy VV
Tpy VV since TpSGp VV
,which is an ideal logic 1 level(2.29)
(2.30)
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Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS Transmission Gate Circuits
Clocking and Dataflow Control
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Basic Logic Gates in CMOS
Digital logic circuits are nonlinear networks that
use transistors as electronic switches to divert one
of the supply voltages VDDor 0 V to the output
The general switching network
Figure 2.18 General CMOS logic gate
Figure 2.19 Operation of a CMOS logic gate
(a)f= 1 output
(b) f= 0 output
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The NOT Gate (1/2)
Figure 2.20 A complementary pair(b) x = 1 input (b) Truth Table
(a) Logic symbol(a) x = 0 input
Figure 2.22 NOT gateFigure 2.21 Operation ofthe complementary pair
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The NOT Gate (2/2)
Figure 2.23 CMOS not gate (b) x = 1 input
(a) x = 0 input
Figure 2.24 Operation ofthe CMOS NOT gate
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The NOR Gate (1/2)
(b) Truth Table
(a) Logic symbol (a) Logic diagram
(b) Voltage network
Figure 2.26 NOR2using a 4:1 multiplexorFigure 2.25 NOR logic gate
Figure 2.27 NOR2 gateKarnaugh map
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NOR (2/2)
Figure 2.30 NOR3 in CMOS
Figure 2.28 NOR2 in CMOS
Figure 2.29 Operational summary of the NOR2 gate
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NAND (1/2)
(b) Truth Table
(a) Logic symbol(a) Logic diagram
(b) Voltage network
Figure 2.32 NAND2using 4:1 multiplexor
Figure 2.31 NAND2 logic gate
Figure 2.33 NAND2 K-map
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NAND (2/2)
Figure 2.36 NAND3 in CMOS
Figure 2.34 CMOS NAND2 logic circuit
Figure 2.35 Operational summary of the NAND2 gate
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Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS Transmission Gate Circuits
Clocking and Dataflow Control
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Complex Logic Gate (2/3)
Figure 2.37 Logic function example
Figure 2.38 pFET circuit for F
function from equation (2.51)
Figure 2.39 nFET circuit for F
Figure 2.40 Karnaugh for nFET circuit
nFET array thatgives F=0 whennecessary
1)(1 cbaF
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Structured Logic Design (1/4)
CMOS logic gates are intrinsically inverting
Output always produces aNOT operationacting on the input variables
Figure 2.42 Origin of the invertingcharacteristic of CMOS gates
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Structured Logic Design (2/4)
Figure 2.43 nFET logic formation
(a) Series-connected nFETs
(b) Parallel-connected nFETs
Figure 2.44 nFET AOI circuit
Figure 2.45 nFET OAI circuit
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Structured Logic Design (3/4)
Figure 2.46 pFET logic formation
(a) Parallel-connected pFETs
(b) Series-connected pFETsFigure 2.47 pFET arrays for AOI and OAI gates
(a) pFET AOI circuit
(b) pFET OAI circuit
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Bubble Pushing
Figure 2.51 Assert-low models for pFETs
(a) Parallel-connected pFETs
(b) Series-connected pFETs
Figure 2.52 Bubble pushing using DeMorgan rules
(a) NAND - OR
(b) NOR - AND
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XOR and XNOR Gates
An important example of using
an AOI circuit is constructing
Exclusive-OR (XOR) and
Exclusive-NOR circuits
bababa
bababa
babababa )(
bababa Figure 2.57 AOI XOR and XNOR gates
(a) Exclusive-OR (b) Exclusive-NOR
Figure 2.58 General naming convention
(a) AOI22 (b) AOI321 (c) AOI221
Figure 2.56 XOR
(2.71)
(2.72)
(2.73)
(2.74)
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Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS Transmission Gate Circuits
Clocking and Dataflow Control
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Transmission Gate Circuits
A CMOS TG is created by connecting an nFET and pFET in parallel
Bi-directional
Transmit the entire voltage range [0, VDD]
1 siffsxy (2.78)
Figure 2.60 Transmission gate (TG)
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Analysis of CMOS TG (1/4)
Four representations of CMOS Transmission Gate (TG)
)(,0
:
:
:
impedancehighZC
SignalControlC
OutputB
InputA
AB
,1
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Analysis of CMOS TG (2/4)
Case (A) Vin=Vdd, C=Vdd(Both transistors ON)
ntDDout
outDDngs
outDDnds
VVVof fTrun
operationNMOS
VVV
VVV
NMOS
,
,
,
,.1
:
:
ntDDout VVVSaturation ,,.2
ptout
DDpgs
DDoutpds
VVSaturation
operationPMOS
VV
VVV
PMOS
,
,
,
,.1
:
:
ptout VVLinear ,,.2
PMOS is always ON regardless of VoutValue
Summary of operating regions of MOS
Vout
Region I Region II Region III
0V |Vt,p| (VDD-Vt,n) VDD
nMOS: saturation
pMOS: saturationnMOS: saturation
pMOS: linear reg.
nMOS: cut-off
pMOS: linear reg.
Total Current fromI/Pto O/P: ID= IDS,n+ISD,pEquivalent resistance of NMOS and PMOS
Equivalent R of TG = reg,n// reg,ppsd
outDDp
nds
outDDn
I
VVreg
IVV
reg,
,,
,,
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Analysis of CMOS TG (3/4)
Region (I): Vout< |Vt,p| {NMOS: saturationPMOS: saturation
2,
)
2,
)(
(2,
)(
)(2,
ptDDp
outDDp
ntoutDDn
outDDn
VV
VVreg
VVV
VVreg
Region (II): |Vt,p| < Vout< (VDD-Vt,n) {NMOS: saturation
PMOS: linear reg.
])())((2[
)(2,
)(
)(2,
2,
2,
outDDoutDDptDDp
outDDp
ntoutDDn
outDDn
VVVVVV
VVreg
VVV
VVreg
(Vgs-Vt) Vds (Vds)2
Note:
NMOS source-to-substrate voltage
= VSB,n= Vout- 0 = Vout
(Body Effect)
PMOS source-to-substrate voltage
= VSB,p= 0 - 0 = 0 (constant)
Vout
Region 1 Region 2 Region 3
0V |Vt,p| (VDD-Vt,n) VDD
nMOS: saturation
pMOS: saturation
nMOS: saturation
pMOS: linear reg.
nMOS: cut-off
pMOS: linear reg.
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Analysis of CMOS TG (4/4)
Region (III): Vout> (VDD-|Vt,p|) {NMOS: cut-offPMOS: linear reg.
)()]()(2[
2,
,,
,
simplifyVVVV
reg
openreg
outDDptDDp
p
n
Total resistance of CMOS TG v.s. Vout
Equivalent resistance of TG is relatively
constant
Individual reg. of NMOS and PMOS are
strongly dependent on Vout!!
Vout
Region 1 Region 2 Region 3
0V |Vt,p| (VDD-Vt,n) VDD
nMOS: saturation
pMOS: saturation
nMOS: saturation
pMOS: linear reg.
nMOS: cut-off
pMOS: linear reg.
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Logic Design using TG (1/3)
Multiplexors
TG based 2-to-1 multiplexor
The 2-to-1 extended to a 4:1 network by using the 2-bit selector word (s 1, so)
sPsPF 10(2.79)
013012011010 ssPssPssPssPF (2.80)
Figure 2.61 A TG-based 2-to-1 multiplexor
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Logic Design using TG (2/3)
TG based XOR/XNOR
TG based OR gate
bababa babababa
(2.81) (2.82)
ba
baa
baaaf
)(
(2.83)
Figure 2.62 TG-based exclusive-OR and exclusive-NOR circuits
(a) XOR circuit (b) XNOR circuit
Figure 2.63 A TG-based OR gate
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Logic Design using TG (3/3)
Alternate XOR/XNOR Circuits
Mixing TGs and FETs which are designed for exclusive-OR and equivalence
(XNOR) functions
Itsimportant in adders and error detection/correction algorithms
Figure 2.64 An XNOR gate that used both TGs and FETs
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Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS Transmission Gate Circuits
Clocking and Dataflow Control
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Clock and Dataflow Control
Synchronousdigital design using a clock signal Simply, the switching characteristics of TGs
As Figure 2.66(b), when TG is off, the value ofy=xfor
a very short time thold. If we use a high-frequency clock
then the periodic open-closed change occurs at every
half clock cycle
Figure 2.65 Complementary clocking signals
Tf
1 (2.84)
Figure 2.66 Behavior of a clocked TG
(a) Closed switch
(b) Open switch
holdtT )2/(
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Clock and Dataflow Control Using TGs
Data Synchronizationusing transmissiongates
To use clocked TGs for data flow control,
we place oppositely phased TGs at the
inputs and outputs of logic blocks
Figure 2.67 Data synchronization using transmission gates
Figure 2.68 Block-level system timing diagram
In this scheme, data moves through alogic block every half cycle
Since the logic blocks are arbitrary, itcan be used as the basis for buildingvery complex logic chains
Synchronize the operations performedon each bit of an n-bit binary word
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A Synchronized Word Adder
In figure 2.69(a), the input word an-1a0andbn-1b0 arecontrolled by the plane,
while the sum sn-1s0 is transferred to the
output when
Every bit in a word is transmitted from one
point to another at the same time, which allowsus to track the data flow through the system
In figure 2.69(b), a larger scale with the ALU
(arithmetic and logic unit)
Input A and B are gated into the ALU by the
control signal The result word Out is transferred to the next
stage when , i.e.,
Figure 2.69 Control of binarywords using clocking planes
clock
0
(a) Clocked adder
(b) Clocked ALU
plane
1 0
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Clock and Dataflow Control
Clocked transmission gates synchronize the flow of signals, but the linethemselves cannot store the values for times longer than thold
Figure 2.70 SR latch
(a) Logic diagram
(b) CMOS circuit
Figure 2.71 Clocked SR latch
(a) Logic diagram
(b) CMOS circuit