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IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 27, NO. 1, FEBRUARY 2004 97

An Efficient Path-Based Equivalent CircuitModel for Design, Synthesis, and Optimizationof Power Distribution Networks in Multilayer

Printed Circuit BoardsYong-Ju Kim, Han-Sub Yoon, Seongsoo Lee, Gyu Moon, Joungho Kim, and Jae-Kyung Wee

AbstractIn high-speed printed circuit boards, the decouplingcapacitors are commonly used to mitigate the power-bus noise thatcauses many signal integrity problems. It is very important to de-termine their proper locations and values so that the power dis-tribution network should have low impedance over a wide rangeof frequencies, which demands a precise power-bus model consid-ering the decoupling capacitors. However, conventional power-busmodels suffer from various problems, i.e., the numerical analyzesrequire huge computation while the lumped circuit models showpoor accuracy. In this paper, a novel power-bus model has beenproposed, which simplifies the n-port Z-parameters of a power-busplane to a lumped T-network circuit model. It exploits the path-based equivalent circuit model to consider the interference of thecurrent paths between the decoupling capacitors, while the con-ventional lumped models assume that all decoupling capacitorsare connected in parallel, independently with each other. It alsomodels the equivalent electrical parameters of the board parasiticprecisely, while the conventional lumped models employ only theinter-plane capacitance of the power-ground planes. Although it isa lumped model for fast and easy calculation, experimental resultsshow that the proposed model is almost as precise as the numer-ical analysis. Consequently, the proposed model enables a quickand accurate optimization of power distribution networks in thefrequency domain by determining the locations and values of the

decoupling capacitors.

Index TermsDecoupling capacitors, equivalent circuit model,power-bus distribution network.

I. INTRODUCTION

IN MODERN digital systems, the operation frequency, thesignal bandwidth, and the power consumption are increasing

while the power supply voltage level and the signal rising time isdecreasing. Power stability becomes more and more importantin the high-speed digital system design, since the power supply

Manuscript received September 1, 2003; revised January 9, 2004. This workwas supported by the Basic Research Program, Korea Science and EngineeringFoundation, under Grant R01-2002-000-00039-0.

Y.-J. Kim is with the Memory Research and Development Division, HynixSemiconductor, Ichon, 467-701, Korea.

H.-S. Yoon is with the Division of Electrical and Computer Engineering,Hanyang University, Seoul, 133-070, Korea.

S. Lee is with the School of Electronic Engineering, Soongsil University,Seoul, 156-743, Korea.

G. Moon and J.-K. Wee are with the Division of Information and Elec-tronics Engineering, Hallym University, Chuncheon 200-702, Korea (e-mail:[email protected]).

J. Kim is with the Department of Electrical Engineering, Korea AdvancedInstitute of Science and Technology, Daejon 305-701, Korea.

Digital Object Identifier 10.1109/TADVP.2004.825481

noise during input/output (I/O) switching often causes voltagefluctuations and circuit delays due to the transient currents in-

jected into the power distribution system [1]. To mitigate thepower supply noise, the surface mount technology (SMT) de-coupling capacitors are commonly used in the multilayer printedcircuit boards (PCB). Consequently, precise modeling of thepower distribution systems is inevitable for signal integrity and

power stability on transient operations [2], which shouldincludeall on-board components such as chips and decoupling capaci-tors.

Conventional power-bus models are categorized into threeapproaches, i.e., the full-wave electromagnetic models, themodified nodal analyzes, and the lumped circuit models. Thefull-wave electromagnetic models are based on the physicalelectromagnetic field equations, and they are solved by numer-ical analyzes. Although they are the most accurate power-busmodels, they consume too much time and computation tosolve electromagnetic equations. Therefore, they are seldomused in practical multiplayer PCB design. The partial elementequivalent circuit (PEEC) model divides a power-bus planeinto unit cells, and convert each unit cell into equivalent resis-tance-inductance-conductance-capacitance (RLGC) elements.The nodal current-voltage equations are established using theseRLGCvalues, and they are solved by numerical analyzes. Theyare much faster than the full-wave electromagnetic models,and their simulation results agree well with the measurements.However, for acceptable accuracy, the number of the unit cellsshould be large, which still requires too much computationalresource.

The lumped circuit models employ proper equivalent modelof a power-bus plane, and they convert whole power-bus planeinto several lumped circuit elements. They are very fast whencompared to the PEEC model, since the number of equivalentcircuit elements is extremely small. Furthermore, they are fullycompatible with the modeling of on-board components such asdigital chips and transmission lines, since most on-board com-ponents are modeled as equivalent passive or active circuit el-ements. When the power distribution network of the PCB andall on-board components are modeled as equivalent circuit ele-ments, the whole system can be simulated using many commer-cial circuit simulation programs such as SPICE. To compare thecomputational complexity of the PEEC model and the lumpedcircuit model, the authors carried out a transient simulation ofa 533 Mb/s double-data-rate (DDR) DRAM module, where a8 256 Mb DRAM chip was mounted on the multilayer PCB

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98 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 27, NO. 1, FEBRUARY 2004

module for evaluation. In the PEEC model, the number of unitcells was 1200, and the simulation time on a workstation was2 h 40 min. On the contrary, in the lumped circuit model, thenumber of the circuit elements was about 30 [3], [4], and thesimulation time on the same workstation was 5 min. In manycases, the lumped circuit models are simple enough to be calcu-lated by pencils.

However, conventional lumped circuit models suffer frominaccuracy. Based on the lumped circuit models, extensiveresearch [3], [4] had been carried out to determine the locationsand values of the decoupling capacitors. Unfortunately, theyusually failed to design reliable power distribution networkfor practical applications, since the designed power-bus showssome errors on impedance over a wide range of frequencies.Most of the conventional models [5], [6] assume that thecapacitors on the PCB are independently connected in parallelbetween power and ground planes, but this is too rough inthe real PCB. Consequently, the current coupling betweentwo measured modes is ignored, which severely degrades theaccuracy.

In this paper, we propose a novel power-bus model includingdecoupling capacitors called the path-based equivalent circuit(PBEC) model. It provides a simple but accurate lumped equiv-alent circuit model for a power distribution network, which es-timates the accurate frequency behaviors of a PCB. It exploitsthe path-based equivalent circuit model to consider the inter-ference of the current paths between the decoupling capacitors,while the conventional lumped models assume that all decou-pling capacitors are connected in parallel, independently witheach other. It also models the equivalent electrical parametersof the board to consider the board parasitic precisely, while theconventional lumped models employ only the inter-plane capac-itance of the power-ground planes.

The proposed PBEC model is briefly described as follows.1) Similar with the conventional models [5], the

power-ground planes are modeled by an array ofsquare unit cells using distributed RLGCelements.

2) At all grid points, the nodal current-voltage equationsare derived from the partial element equivalent circuitapproach for general multilayer dielectric layers by en-forcing Kirchoffs Current Law (KCL).

3) The nodal admittance matrix is obtained from the nodalequations, and the Z-parameters at all nodes are obtainedby calculation the inverse matrix of the nodal admittancematrix.

4) Considering the current paths of decoupling capacitors,

the inductance and resistance based on the lumped modelapproximation are calculated as functions of distancefrom one port (=chip) to the other port (=decoupling ca-pacitor) with T-network model of two-port z-parameters.

5) The board parasitic is extracted from its self-impedanceat the location of the chip.

Steps 4) and 5) are the major contributions of the proposedmodel. Conventional design approaches based on the PEECmodel should solve the modified nodal equations in manyiterations, but the proposed PBEC model needs to solve itonly once for obtaining the Z-parameters at all nodes of thepower distribution network on a PCB. The lumped circuitmodel is derived with the Z-parameter matrix obtained from

Fig. 1. Typical digital circuit system with multilayer PCB.

the modified nodal analysis by simple calculation, so it needsto solve the modified nodal equation only once over the designprocedure of the power distribution network.

The rest of the paper is organized as follows. Section II de-scribes the impedance calculation of the power-bus plane. Thelumped equivalent circuit model of the power-ground planes isproposed in Section III. Experimental results are shown in Sec-tion IV, and Section V concludes the paper.

II. IMPEDANCE CALCULATION OF POWER-BUS PLANE USINGMODIFIED NODAL ANALYSIS

In general, it requires much computation to design the powerdistribution network of the high-speed digital system. It alsotakes too long time to perform the time domain simulation ofdigital systems to compute the PEEC model of the designedpower distribution network. In this paper, we propose a novellumped circuit model called the PBEC model, which is usefulto design a high-speed digital system from the early-stage de-

sign. The Z-parameter matrix of power planes is needed to gen-erate the proposed PBEC model, which is obtained from themodified nodal analysis, the plane resonant model or the mea-surement of vector network analyzer. In this paper, the modifiednodal analysis is used for obtaining the Z-parameter matrix ofpower planes. Using the Z-parameter matrix, the PBEC modelcan be directly derived for all power distribution networks in-cluding mounted decoupling capacitors. By using the proposedPBEC model, the circuit simulations of on-board chips consid-ering a power distribution network also can be easily carried outwithout much computation.

Fig. 1 shows a typical digital system with a multilayer PCB.Most on-board components such as chips, decoupling capaci-

tors, and registers are mounted on the first layer and the lastlayer. Power planes of (or ) and GND pairs can beallocated both with inner or outer layers, but they are usuallydistributed in the inner two layers. As reported in [5] and [6],the lumped local decoupling capacitors connecting thepins of digital ICs to ground plane often provide a return passof high frequency energy. A low impedance power distributionnetwork, which consists of the distributed /GND parallelplanes and the lumped decoupling capacitors, is the key factor tosuccessfully reduce the ground bounce noise in the high-speedPCB. Fig. 2 shows a generic design flow of a digital PCB afterthe board size and its stack-up are determined. The detailed se-quence is explained as follows.

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KIM et al.: EFFICIENT PATH-BASED EQUIVALENT CIRCUIT MODEL 99

Fig. 2. Generic design flow of a digital PCB.

1) Operating power of the whole system is given, and the

target impedance of the board is calculated.

2) The impedance of power-ground planes based on the

power distribution network is calculated.

3) Considering the signal connections, each chip location is

determined on the board.

4) For each path from a chip to all net points on the board,the inductance and resistance are calculated as a function

of distance.

5) The numbers, locations, and values of decoupling capaci-

tors are determined and allocated so as to satisfy the target

board impedance.

In the PCB design process, one of the key issues is the pre-

cise modeling of a power distribution network, since it is closely

related with the board impedance of the designed PCB. Many

commercial PCB design tools estimate the frequency behavior

of the PCB using the PEEC methods. As reported in [7], they

can be quite effective to model the power distribution network

with decoupling capacitors, but they require too much computa-tional resource as described in the introduction. In this paper, a

precise but simple lumped circuit model is proposed to analyze

the power distribution network, which has the following advan-

tages in the PCB design.

1) It is possible to predict all parallel resonant frequencies

of all components on the whole board system, including

practically interesting cases such as vias.

2) It is much faster than the conventional PEEC methods in

the early PCB design stage.

3) It is possible to simulate whole board system, i.e., it can

simulate power distribution network and on-board com-

ponents together.

Fig. 3. Unit cell model for a power-groundplane. (a) Segmentationof a powerplane. (b) PCB layers of a unit cell. (c) Equivalent circuit of a unit cell.

4) It enables to simulate the frequency response of the board

using conventional circuit simulators such as SPICE. Inmany cases, it needs no complicated software programs at

all, since it is simple enough to be calculated by pencils.

5) It can be applied to many other applications such as board

optimization tools.

A. Unit Cell Model for Power Distribution Network

In a typical multilayer PCB as shown in Fig. 1, the power-

ground planescan bemodeled by dividing itinto an array

of unit cells. Fig. 3(a) shows the structure of a two-dimensional

array of unit cells, which has and cells in - and -direc-

tions, respectively. A unit cell is shown in Fig. 3(b), where top

and bottom layers are power and ground planes, respectively.

The unit cell size determines the model precision and the overallsimulation time. Based on the effective electrical length of the

signals, the unit cell size is obtained as (1), where is the

relative dielectric constant of FR-4, is the speed of light in

vacuum, is the pulse rise time, and is the number of unit

cells. In general, is over 50 to obtain high accuracy [8]

m (1)

Fig. 3(c) shows an equivalent circuit of a unit cell. Its RLGC

values are derived as follows [8]. The capacitance between

two parallel plates is given as (2), where is the distance be-

tween two parallel plates

(2)The inductance is the sum of the internal inductance and

the external inductance, but the internal inductance is usually

negligible on the PCB. The velocity of electromagnetic wave

traveling between the plates is given as (3), where is the light

speed in vacuum. The external inductance is the parallel plate

inductance in (3), and it is obtained as (4). Note that the ca-

pacitance and the inductance are independent of the oper-

ating frequency

(3)

(4)

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Fig. 4. Equivalent circuit model of a power-ground plane.

The resistance is the function of the operating frequency

and is obtained as (5) and (6), where , , and are the skin

depth, resistivity, and thickness of the conductor, respectively.

The skin depth is given as (7), where is the magnetic per-

meability of the conductor. Dielectric loss is the function of

the operating frequency and the capacitance and is obtained

as (8), where is the loss tangent of the conductor with the

measured value of 0.02 in this paper

(5)

(6)

(7)

(8)

The RLGC equivalent circuit model of a unit cell shown in

Fig. 3(c) is similar with the lossy subcircuit in [9]. As shown

in Fig. 3(a), the power-ground planes are modeled by extending

the unit cells into -and -directions. At the boundary of the

planes, and have half values of center cells, and

and have double values of center cells since the edge cells do

not have common elements with other cells.

B. Nodal Equations for Power Distribution Network

As shown in Fig. 4, a network of equivalent circuits for

power-ground planes can be modeled as an array of

unit cells [10]. An equivalent circuit of the unit cell can be

represented by series impedance and parallel admittance

as

(9)

To obtain z-parameters of the equivalent circuit of the power-

ground planes, the nodal admittance matrix is constructed for

the equivalent circuit of Fig. 4. The currentvoltage equationsof each node are obtained as (10a) to (10i), where and

are the nodal current and voltage of a node for admittance

, respectively.

(10a)

(10b)

(10c)

(10d)

(10e)

(10f)

(10g)

(10h)

(10i)

From (10a) to (10i), the nodal matrix of the power distribution

network is obtained as (11), where is the nodal admit-

tance matrix with the size of , and and are the

nodal current vector and the nodal voltage vector, respectively

(11)

The modified nodal analysis solves (11) using numerical

analysis and estimates the frequency behavior of the power dis-

tribution network. To evaluate the modified nodal analysis, its

simulation results were compared with the measured data from

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Fig. 5. Comparison of the modified nodal analysis and the measurement.(a) Test pattern. (b) Self-impedance of the power-ground plane at port B1.

vector network analyzer (VNA). The authors fabricated a test

board of 11 7 cm as shown in Fig. 5(a). The power-ground

planes are made with Cu and the dielectric is FR4 with a relative

dielectric constant of 4.5. The distance between power and

ground planes is 122 m. Fig. 5(b) shows the self-impedance

of port B1, where the simulation result agrees well with the

measured data.

When a decoupling capacitor is attached to a node, the ad-

mittance in current-voltage equation of the node becomes

(12), where is the capacitance of the decoupling capacitor,

is the sum of the inductance of the via and the effec-

tive series inductance (ESL) of the decoupling capacitor, and

is the sum of the resistance of the via and the effective

series resistance (ESR) of the decoupling capacitor. Applying

an independent source to a node of network, the matrix for the

modified nodal analysis can be constructed

(12)

Fig. 6. Lumped T-network model with two-port z-parameters.

III. PATH-BASED EQUIVALENT CIRCUIT (PBEC) MODEL OF

POWER-GROUND PLANES

As described earlier, the modified nodal analysis in Section II

requires too much computational resource, since the current-

voltage equations of (11) can be solved only by numerical anal-

ysis. The modified nodal analysis can achieve the accurate de-

sign through iterative simulations according to considerations

of all placements and values of decoupling capacitors. However,

this approach severely suffers from huge computation resource

needed to design the power distribution network. On the con-

trary, the lumped circuit model is derived with the Z-parameter

matrix, which needs to solve the modified nodal equations only

once to designthe powerdistribution network. In this paper, (11)

is simplified to a lumped circuit model with equivalent induc-

tances and resistances, which is simple enough to be solved by

pencils.

A. Equivalent Circuits of T-Network Model

For precise estimation of the impedance, the proposed

lumped equivalent circuit model should reflect various pa-

rameters such as the board size, the relative location of the

decoupling capacitors or the chips on the board, and the

distance between the measured points. When two arbitrary

locations on the board are considered, e.g., port1 (chip) and

port2 (decoupling capacitor), the effects of all circuits and

decoupling capacitors are modeled as a T-network circuit as

shown in Fig. 6. and represent the impedance part with

inductance and resistance, and represents the admittance

part with capacitance and conductance. When the two-port

analysis is applied to the T-network circuit in Fig. 6, the

two-port z-parameters , , , and , and the T-net-

work parameters , , and are obtained as (13) and (14),

respectively

(13)

(14)

In this paper, the effective impedance is called as the

forward-path impedance between port1 and port2, since current

flowing forward from port1 to port2 makes the voltage

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difference when the port2 voltage is open. Similarly, the ef-

fective impedance is called as the backward-path impedance

between port1 and port2, since current flowing backward

from port2 to port1 makes the voltage difference when the

port1 voltage is open. and are approximated as (15)

with lumped resistance and inductance. From (14) and (15),

the equivalent lumped resistance and and inductance

and are obtained as (16)(15)

(16)

In (16), the lumped resistance and and inductance

and are expressed in terms of two-port z-parameters ,

, , and . When the locations of port1 (chip) and port2

(decoupling capacitor) are given, the z-parameters , ,

, and are calculated by solving the currentvoltage equa-tions of (17). The port impedance matrix of the power

distribution network with the size of is an inverse

matrix of the nodal admittance matrix in (11)

(17)

As described in Section II-A, inductance and are

frequency-independent, while resistance and are

frequency-dependent. However, and are over-

whelmed by inductive impedance of and at frequencies

above the resonant frequency, and they are also overwhelmed

by capacitive impedance of the bare board at frequencies below

the resonant frequency. It means that and are

dominant in the bare board impedance only near the resonant

frequency and they are negligible at other frequencies. There-fore, and are approximated as the resistance

values and at the first resonant frequency ,

and they are used as the frequency-independent values and

for all frequencies. In this approximation, the errors are

negligible in the impedance of the power distribution network.

The board parasitic is modeled as the self-impedance of a bare

board at the first resonant frequency of the bare board ,

and it is obtained as

(18)

where is given as .

Described indetail, the board parasitic resistance can

be obtained from magnitude of the first series resonance. At that

point, the magnitude of the board impedance has only the resis-

tance out of board parasitic. can be obtained directly

from the area of power plane. also be easily calculated

from relation between the resonant frequency and the capaci-

tance.

B. Interference of Current Paths Between Decoupling

Capacitors

On the power-ground planes, the current propagates just like

a radial wave with radius . As a result, the current should be

Fig. 7. Proposed lumped circuit model of two decoupling capacitors.(a) Bare board. (b) Decoupling capacitor . (c) Decoupling capacitor

. (d) Decoupling capacitor and . (e) Determination of .(f) Determination of .

equal at two different locations on the power planes, as long as

the distance from a view port is equal. Fig. 7(a) (c) illustratesthe current on the power planes and the corresponding T-net-

work model in case of a bare board, a decoupling capacitor

on a board, and a decoupling capacitor on a board, respec-

tively. , , , , , , , , and

denote a view port, self-impedance and inter-plane capacitance

of a bare board, three T-network parameters of , and those of, respectively. , , , , and denote the dis-

tance from to , the distance from to , the current

from , the current through , and the current through ,

respectively. When there are two decoupling capacitors and

on a board, Fig. 7(b) and Fig. 7(c) are merged into Fig. 7(d).

The current is equal at and since the distance from

is equal. Consequently, the current flowing into is changed

from to . This means that the current path from

to interferes the current path from to . In general,

the current path of inner ( closer from view port) location in-

terferes the current path of outer ( farther from view port) loca-

tion. This interference was never considered in the conventional

lumped circuit models, since they assumed parallel-independent

current paths. In this paper, we propose a novel lumped circuit

model fully considering the interference of current paths as fol-

lows.

When the T-network modelsof Fig. 7(b) and (c) arecascaded,

is replaced to , , and . The current path from

to is interfered by the current path from to , so

the corresponding equivalent circuit value should be modified

from to . is rewritten as , since it represents

theboardparasitic. , , and remain unchanged. When

is open (i.e., is removed from the board), the equivalent

circuit of Fig. 7(e) should be identical to that of Fig. 7(c), which

leads to . Similarly, the equivalent circuit

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Fig.8. Comparison between the conventional models and the proposedmodel.(a) Conventional model in [3]. (b) Conventional model in [4]. (c) Proposedmodel.

Fig. 9. Generalized lumped circuit model of decoupling capacitors.(a) Generalized n-port equivalent circuit network. (b) Conventional model in[3]. (c) Conventional model in [4]. (d) Proposed model.

of Fig. 7(f) should be identical to that of Fig. 7(a) when and

are open, which leads to .

The conventional models and the proposed model are com-

pared in Fig. 8. The conventional model in [3] does not consider

the distance between view port and the decoupling capacitors.

As shown in Fig. 8(a), the decoupling capacitors are modeled as

location-independent circuit parameters, and the power-ground

plane is modeled as a pure capacitance only. Therefore,

Fig. 10. Extracted inductance from the proposed model. (a) Test pattern.(b) Pad-to-pad distance and extracted inductance.

Fig. 11. Test pattern to evaluate the proposed model.

and are not expressed as functions of distance, and the cur-

rent flowing into is overestimated by , and the board

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(a) (b)

(c) (d)

(e)

Fig. 12. Equivalent circuit model of Fig. 11. (a) Proposed model with four decoupling capacitors at (E1, E2, E3, E4). (b) Model in [4] with four decouplingcapacitors at (E1, E2, E3, E4). (c) Proposed model with 4 decoupling capacitors at (E1, N1, W2, S2). (d) Model in [ 4] with four decoupling capacitors at (E1, N1,W2, S2). (e) Model in [3] with four decoupling capacitors at (E1, E2, E3, E4) or (E1, N1, W2, S2).

parasitic is not precisely modeled. Conventional model in [4]

considers the distance between view port and decoupling ca-

pacitors, and it also considered the parasitic series impedance

of a board. However, it assumes that all decoupling capacitors

are independently connected in parallel and the power-groundplane is modeled as a pure capacitance only, as shown

in Fig. 8(b). The can be expressed as in T-network

model where the is the impedance between the view port and

the th capacitor. Therefore, the current flowing into is still

overestimated by , and the board parasitic is not precisely

modeled yet. Note that in Fig. 8(c), the proposed model [ 11]

precisely calculates the current flowing into . Also note that

the proposed model calculates the board parasitic , while the

conventional models ignore it.

Above examples of two decoupling capacitors are general-

ized in Fig. 9. The power distribution network including de-

coupling capacitors is modeled as an -port equivalent circuit

network, as shown in Fig. 9(a). The conventional models in [3]

and [4] are represented as parallel-connected circuits, as illus-

trated in Fig. 9(b) and (c), respectively. The proposed model is

shown in Fig. 9(d). and are calculated similarly with

the case of two decoupling capacitors, and they are obtained as(19) and (20), where is the T-network parameter of th de-

coupling capacitors sorted by ascending order of the distance,

and is the self-impedance of a bare board

(19)

(20)

IV. EXPERIMENTAL RESULTS

To illustrate the effects of both the location of measured ports

and the distance from measured ports, a test board was designed

as shown in Fig. 10(a). The paired ports have different locations

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Fig. 13. Comparison of computed input impedance. (a) Four decouplingcapacitors at (E1, E2, E3, E4). (b) Four decoupling capacitors at (E1, N1, W2,S2).

and distances from 2 to 10 cm with the pad size of 1 1 cm.

Fig. 9(b) shows the extracted inductances between paired portsfrom (A1, B1) to (A5, B5) exploiting the proposed model. The

distance apparently affects the inductance between the paired

ports, since and increase along with the distance. In ad-

dition, the paired ports (A5, B5) show the effect of locations of

the measured port. Roughly speaking, and showlinear in-

crease. However, when the port Bi goes toward the board edge,

and increase more than linearity and their difference be-

come diminished due to the effect of the board edge.

To evaluate the proposed model, another test board was de-

signed as shown in Fig. 11, where a chip locates in the center of

the board. To simulate the effect of the distances and locations,

two copies of the test board in Fig. 11 were fabricated, and two

different sets of decoupling capacitors were mounted on eachboard. These sets have same capacitance values but different lo-

cations. Set 1 consists of four decoupling capacitors, i.e., E1,

E2, E3, and E4 with the values of 5, 20, 220, and 470 nF and

the distance of 10, 20, 30, and 40 mm from the chip, respec-

tively. Set 2 consists of four decoupling capacitors, i.e., E1, N1,

W2, and S2 with the values of 5 nF, 20 nF, 220 nF, and 470 nF

and the distance of 10 mm, 10 mm, 20 mm, and 20 mm from

the chip, respectively. The equivalent circuit models are shown

in Fig. 12. The proposed model is a lumped and partially dis-

tributed model as shown in Fig. 12(a) and (b), where the board

parasitic is modeled with the same method as the decoupling ca-

pacitors. The conventional model in [4] is shown in Fig. 12(c)

and (d), where the decoupling capacitors are modeled as inde-

pendently parallel current paths. Fig. 12(e) shows the conven-

tional model in [3], which ignores the distances and locations

of the decoupling capacitors. The board parasitic is ignored in

the conventional models in [3] and [4].

Fig. 13 shows the magnitude of input impedances for set

1(E1, E2, E3, E4) and set 2 (E1,N1, W2, S2).In Fig. 5,the mod-

ified nodal analysis was proven to agree well with the real mea-surement, so the simulation results of the modified nodal anal-

ysis was compared with the computed input impedances from

the conventional models and those from the proposed model.

As shown in Fig. 13, the proposed model agrees well with the

modified nodal analysis, while conventional models in [3] and

[4] differ a lot. However, even the proposed model cannot pre-

cisely estimate multiple resonances in high-frequency ranges,

which should be studied thoroughly in future works.

V. CONCLUSION

This paper presents a simple and accurate model of power-

ground planes including decoupling capacitors. It models thepower distribution network as the -port z-parameters, and sim-

plifies them to a lumped T-network circuit model. It exploits the

path-based equivalent circuit model to consider the interference

of the current paths between the decoupling capacitors, and it

also models the equivalent electrical parameters of the board

parasitic, while the conventional models fail to consider them.

Although it is a lumped model, experimental results show that

the proposed model is almost as accurate as the numerical anal-

ysis. The proposed model is very useful in high-speed digital

PCB design, because it enables a fast and precise simulation of

the power distribution network combined with other on-board

chips and components. The proposed model can be easily ap-

plied to many commercial high-speed system design tools andtime-domain analysis tools.

REFERENCES

[1] J. Kim and M. Swaminathan, Modeling of irregular shaped power dis-tribution planes using transmission matrix method, IEEE Trans. Adv.Packag., vol. 24, pp. 334346, Aug. 2001.

[2] D. Herrell and B. Becker, Modeling of power distribution systems forhigh performance microprocessors, IEEE Trans. Adv. Packag., vol. 22,pp. 240248, Aug. 1999.

[3] L. Smith, Decoupling capacitor calculations for CMOS circuits, inProc. IEEE Conf. Elect. Perform. Electron. Packag., Nov. 1994, pp.101105.

[4] T. Hubing, J. Drewniak, T. Van Doren, and D. Hockanson, Power busdecoupling on multilayer printed circuit board, IEEE Trans. Electro-

magn. Compat., vol. 37, pp. 155166, May 1995.[5] J. Fan, J. Drewniak, S. Hao, and J. Knighten, Quantifying SMT decou-

pling capacitor placement in dc power-bus design for multilayer PCBs,IEEE Trans. Electromagn. Compat., vol. 43, pp. 588598, Nov. 2001.

[6] T. Tarvainen, Simplified modeling of parallel plate resonances on mul-tilayer printed circuit boards, IEEE Trans. Electromagn. Compat., vol.23, pp. 284289, Aug. 2000.

[7] J. Fan, J. Drewniak, S. Hao, and J. Knighten, DC power-bus modelingand design with a mixed-potential integral-equation formation andcircuit extraction, IEEE Trans. Electromagn. Compat., vol. 43, pp.426436, Nov. 2001.

[8] L. D.D. Smith, R. Anderson, and T. Roy, Power plane SPICE modelsand simulated performance for materials and geometries, IEEE Trans.

Adv. Packag., vol. 24, pp. 277287, Aug. 2001.[9] I. Novak, Lossy power distribution network with thin dielectric layers

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[10] K. Lee and A. Barber, Modeling and analysis of multichip modulepower supply planes, IEEE Trans. Comp., Packag., Manufact. Technol.

B, vol. 18, pp. 628639, Nov. 1995.[11] Y.-J. Kim et al., A new circuit model for power plane considering

decoupling capacitances in multi-layer digital applications, in Proc.IEEE Elect. Perform. Electron. Packag., Monterey, CA, Oct. 2002, pp.187190.

Yong-Ju Kim received the B.S., M.S., and Ph.D. degrees in physics fromHanyang University, Seoul, Korea in 1992, 1995, and 2000, respectively.

Currently, he works for Hynix Semiconductor, Ichon, Korea, where he de-signs and optimizes power delivery, interface circuits, and bus interface in high-speed DRAM. His research interests include power delivery design methods ofSOC, high-speed digital system design, and related circuits design.

Han-Sub Yoon receivedthe B.S.degree fromHanyangUniversity,Seoul,Koreain 1978, the M.S. degree from the University of Maryland, College Park, in

1986, and is currently pursuing the Ph.D. degree from Hanyang University, allin electrical engineering.From 1987 to 2002, he worked for Hynix Semiconductor, Ichon, Korea,

where he was a Chief of Technical Staff in the Device Physics Department.Since 2002, he has been a Chief Technical Officer with SamA Informationand Communication Company, Seoul, Korea. His research interests includemodeling and characterization, TCAD simulation, high-performance ESDstructures, advanced interconnect modeling, and the fundamental degradationmechanisms in deep submicron MOS transistors.

Seongsoo Lee received the B.S, M.S., and Ph.D. degrees in electrical engi-neering from Seoul National University, Seoul, Korea, in 1991, 1993, and 1998,respectively.

From 1998 to 2000, he was a Research Associate with the Institute of Indus-trial Science, University of Tokyo, Tokyo, Japan. From 1998 to 2002, he was aResearch Professor in the Department of Information Electronics Engineering,Ewha Womans University, Seoul. Since 2002, he has been an Assistant Pro-fessor in the School of Electronics Engineering, Soongsil University, Seoul. Hisresearch interests include low-power VLSI systems, low-power wireless com-munications, multimedia signal processing, high-speed circuits, and signal in-tegrity.

Gyu Moon received the B.S. degree from the Department of Control and In-strumentation Engineering, Seoul National University, Seoul, Korea, in 1982and the M.S. and Ph.D degrees in electrical engineering and computer sciencefrom George Washington University, Washington, DC, in 1990 and 1993, re-spectively.

From 1982 to 1988, he was with the Electronics and TelecommunicationsResearch Institute (ETRI), Seoul. In 1993, he joined the faculty of the Collegeof Information and Electronics Engineering, Hallym University, Chuncheon,Korea, where he is currently an Associate Professor. In 1986, he was a Visiting

Professor with West Australia University, Adelaide, Australia. His research in-terests include VLSI design, low-power circuits, simultaneous switching noise,and signal integrity.

Joungho Kim received the B.S.and M.S.degrees in electricalengineering fromSeoul National University, Seoul, Korea, in 1984 and 1986, respectively, andthe Ph.D degree in electrical engineering from the University of Michigan, AnnArbor, in 1993.

During his graduate study, he was involved in femtosecond time-domain op-tical measurement technique for high-speed device and circuit testing. After re-ceiving the Ph.D. degree, he moved to Picometrix, Inc, Ann Arbor, in 1993 asa Research Engineer, where he was responsible for development of picosecondsampling systems and 70-GHz photo-receivers. In 1994, he joined the MemoryDivision, Samsung Electronics, Kiheung, Korea, where he was engaged in Gbit-scale DRAM design. In 1996, he moved to the Korea Advanced Institute ofScience and Technology (KAIST), Taejon, Korea, where he is currently an As-sociate Professor with the Electrical Engineering and Computer Science De-partment. Since joining KAIST, his research centers on modeling, design, andmeasurement of high-speed interconnection, package, and PCB. His researchtopic includes design issues of signal integrity, power/ground noise, and ra-diated emission in high-speed SerDes channel, system-in-package (SiP), andmultilayer PCB. He was on sabbatical leave during academic year from 2001to 2002 at Silicon Image Inc., Sunnyvale, CA, as a Staff Engineer, where hewas responsible for low noise package design of SATA, FC, and Panel LinkSerDes devices. He has authored or co-authored over 100 technical articles andnumerous patents.

Dr. Kim has been served as the Chair or Co-chair of the EDAPS Workshopsince 2002.

Jae-Kyung Wee received the B.S. degree in physics from Yonsei University,Seoul, Korea, in 1988, and the M.S. degree in physics and the Ph.D. degree in

electrical engineering from Seoul National University, in 1990 and 1998, re-spectively.

From 1990 to 2001, he worked for Hynix Semiconductor, Ichon, Korea,where he was a Project Leader of 1-G DDR SDRAM using 0.13m technology.Since 2001, he has been an Assistant Professor in the College of Informationand Electronics Engineering, Hallym University, Chuncheon, Korea. Hisresearch interests include interconnection modeling, charge pump, DLL, I/O,module design, and signal integrity for high-speed chips.

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