Geometric Programming Based Power-Delay Optimization using Transistor-Sizing for Submicron and

Deep Submicron CMOS Inverter Manisha Pattanaik and Swapna Banerjee

Department of E & ECE, Indian Institute of Technology, Kharagpur-721 302, INDIA i nan ish3kL .ecc . i i t l -~ .~~c t . i n , swapna@ece.iitkgp.emet.in

Abstruci-This paper proposes a new method to formulate the transistor sizing problem as a geometric programming by using a modified I-V model in the power-delay product (PDP), for sub micron and deep sub micron CMOS inverter circuit. The design objective and constraints are modeled as posynomial functions of the design variables. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (0.25-~m).results. Further the approach has been extended to predict the transistor siring for deep submicron (0.09- pm) CMOS inverter.

1. INTRODUCTION

Transistor sizing is the operation of enlarging or reducing the channel width of the transistor. I t is an effcctive technique to improve the dclay of a CMOS circuit. When the channel width is increased the current drive capability increases, which reduces the signal riseifall times at the gate output. Thc area occupied by the transistors increases with increased transistor sizcs and may increase the layout area. Transistor sizes are the most important factor affecting the area, performance and power dissipation of a circuit comprising transistor network. The complexity of transistor sizing is due to the fact that each transistor could potentially introduce one dimension to the problem. In some cases simple analytical models can be used: But there is no analytical model that can be applied to a large classofcircuits [ I ] .

Several approaches have been suggested in literahre [Z], [3] that perform optimization for area, delay and power of digital CMOS circuits. Analytical equation based optimization requires the evaluation of circuit pcdormances by using analytical equations. The closed fonn delay expression for the CMOS inverter circuit based on the alpha power law MOS model [4] includes the camier velocity saturation effect for short channel devices. But it is not giving accurate results particularly for nanoscale MOSFET devices (below 100nm). Further it has been observed that though the model proposed by Yutao Ma et. al [ 5 ] performed well up to 90 nm MOSFET, the output characteristics for current voltage inodel dcviates from the experimental results when both V,, and

Vdr are high. A direct approach for transistor sizing is to minimize the power consumption of a circuit subjected to a delay constraint. For such an approach to bc applicable, particularly in deep sub micron regime, a reliable model for power consumption of a CMOS inverter circuit with respect to transistor sizing is essential. The objective of this paper is to develop the power-delay product (PDP) model by using a compact I-V model proposed in [ 6 ] , [7] which performs well for nanascale MOSFET devices.

The main purpose of developing the transistor sizing tool is to explore the most ideal design solution at which the circuit satisfies thc required specification and at the same time the power delay product (PDP) is optimized. The power delay product (PDP) function is non-linear in nature, the coefficients of the terms are positive and the exponents are not restrictcd to positive integers. So a posynomial geometric programming (GP) approach is proposed. Geometric programming is a special optimization technique which is marked by its extreme efficiency and truly global charactcristics 121, 131, 181, 191. GP has been used recently to optimally design electronic circuits including CMOS op-amps 131, transistor sizing of CMOS circuits [8], 191.

The paper is organized as follows. Section 2 dep'icts the modified power-delay model 161. Section 3 proposes a geometric programming model with its solution. Section 4 analyses the results of thc proposed posynamial FP. Section 5 summarizes the paper.

2. MODtFlED POWER-DELAY MODEL

In order to analyze the operation of a CMOS inverter far calculating the power, delay and power-delay product for different frequencies and load capacitances, an input ramp with transition time 'Y is applied to a CMOS invener. The problem in this paper is focused on the dynamic power dissipation of a CMOS inverter circuit.

The MOSFET drain cumnt equation used for inverter analysis is given in [6 ] as

I , = 0, V, < V,, (Cut off region) ( I )

Computer-aided Design and Testing /485

where z=n for NMOS transistor and z=p for PMOS

transistor. P,, = B,C,, - and P, = B_C,, - are the transistor gain factor of the MOSFET device in linear region and in saturation region respectively. B_

and B,, are used to control the characteristics of the saturation region and linear region respectively as discussed in [6].

The detail analysis for fast input and slow input ramp i s discussed in [6 ] . The switching operation of CMOS inverter is analyzed to determine its propagation delay. By including the modified carrier mobility proposed in [5], the propagation delay (t,) is expressed as

w* Wi L, L,

In the above expression, x is the technological factor [6] depends on the channel length and gate oxide thickness (b,). So, the dynamic PDP expression can he represented as follows.

The major focus of this paper is to minimize the PDP, subjected to the constraints of the total output load capacitance and the sizes (width) of NMOS and PMOS transistors used in a simple inverter circuit.

3. GEOMETRIC PROGRAMMING MODEL The proposed geometric program (GP) model can be expressed by rearranging the terms in the objective function and the constraints and is given by the form

subiected to

and the non-negativity condition w w,, and C , 2 0 and a , b, a l , ai, a,, a4 are technology dependent parameters.

Since, the above problem is non-linear in nature and the exponents ( positive and negative) of the variables do occur in the expressions, it can he cast as a geometric program [10][11][12]. By solving (6). (7) and (8), the optimum ratio of transistor sizes for minimum PDP is as follows:

I '

where woI and wu2 are the contributions of the first and second terms in the objective function.

4. RESULTS AND DISCUSSION The geometric program developcd by using modified I-V model [6] for minimizing PDP has been solved for transistor sizing. 0 . 2 5 . ~ CMOS technology is used for inveiter analysis. The solution of geometric program problem suggests that tlie expression for optimum transistor sizing ratio for minimum PDP is indepcndent of load capacitance at any operating frequency. Comparison of the model results with the Spectre SPICE simulation results [Figure I ] reveals that this ratio approximately stabilizes at 2.2 for 0.25-pm technology. This result can bc predicted accurately within the operating rangc of frequency and load capacitance with marginal error [Table. I and Table. 21. Further it has been observed that the sizes of PMOS and NMOS transistors are increasing almost linearly with the load and frequency to maintain same minimum PDP which closcly inatchcs with the Spectre SPICE simulation results [Figure 2 and Figure 31. This proves the validity of the modified I-V model [6] within the operating frequency and load by considering only the dynamic power dissipation. The proposed GP model behaves well for submicron (0.25pm) CMOS inverter.

Our study has further been extended to predict valucs Ibr deep sub micron range (below 101) om). Thc optimum transistor sizcs for valying luad and operating frequency for minimum PDP through geometric programming are plotted for 0.25 pn in Figure 4 and Figure 5 and for 0.09 pin in Figure 6 and Figure 7. It is observed that though the rate of increase in size for 0.09pm technology is almost same with 0.25pm technology. the driving capability of the circuit with minimum size transistors is more in comparison to 0.25pm. Further i t has been revcslcd that [Table. 31, a 0.25pm CMOS inverter can drive a inaninitmi load of 50ff at 250MHz input frequency, whereas a 0.09pm CMOS inverter can drive a maximum load of 15OfF for the same operating frequency. The maximum switching frequency with the ininimum size for 250MHz input frequency is found to he 450 MHz for 0.25pm and about 535MHz for0.09pm.

5. CONCLUSION A new power-delay posynoinial geomctric program inodcl has been proposed for CMOS inverter, which is hctter suited for modem technologies. The dynamic PDP hac been minimized by considering the major factors dyiiamic power, delay and area by putting limits on transistor width and output voltage swing coupled with input load capacitance. The proposed transistor-sizing problem can handle a wide variety of specifications and constraints, which is extremely fast and results in globally optimal design with marginal error. An important point in judging the correctness of our model is the correspondence of the model delay of a sized circuit with that of its SPICE delay.

T f NCON 2003 I486 ACKNOWLEDGMENT

This work is partially supported by INTEL, Portland, USA.

Table.1: Comparison of Model delay with SPICE delay for 0.25-pm technology (Chd=50 fF)

REFERENCES [ I ] Gary K. Yeap, Practical low power digital VLSl design, Kluwer Academic Publishcr, MA, 1998.

[2] P. Mandal and V. Visvanathan, CMOS op-amp sizing using a geometric programming formulation, IEEE Trans. on Computer- Aided Design of Integrated Circuits and Systems. January 2001,Vol. 20, No.1, pp. 22-38.

[3] M. M. Hershenson, S. P. Boyd and T. H. Lee, GPCAD: A tool for CMOS op-amp synthesis, Table.2 Comparison of Model delay with SPICE delay Proceedings of International Conference on Computer- Aided Design, 1998. pp. 296-303.

[4] T. Sakurai and A. R. Newton, Alpha power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE Journal of Solid State Circuits, Vol. 25, pp. 584-594.

[SI Yutao Ma, L. Liu, L. Tian, Z. Yu and Z. Li, Analvtical charee control and I-V model for

for 0.25-pm technology (Input frequency=500MHz)

- submicrometer and deep sub micrometer MOSFETs fully comprising quantum mechanical effects, IEEE Trans on. Computer-Aided Design, April 2001, .V,l. 20, No.4, pp. 495.502.

[6] M. Pattanaik and S. Banerjee, A new apptoach to analyze a sub-micron CMOS inverter, 16Ih IEEE- International Conference on VLSl Design, January 2003, ISBN 0-7695-1868-0, pp. 116-121.

[7] M. Pattanaik and S. Banerjee, A new approach to model the I-V characteristics for nanoscale MOSFETs, . accepted for presentation at the 2003 International VLSl Symposium on Technology, Systems and Applications to be held at Taiwan [in press).

[SI S. S . Sapatnekar, V. B. Rao, P. M. Vaidya, and S . M. Kang, An exact solution to the transistor sizing problem for CMOS circuits using convex optimization, IEEE Trans. on Computer-Aided Design, Nov. 1993, Vol. 12, pp. 1621-1634.

[9] J. P. Fishburn and A. E. Dunlop. TILOS: A posynomial programming approach to transistor sizing, Proceedings of International Conference on Computer Aided Design, 1995, pp. 326-328.

[IO] R. J. Dufiin, E. L. Peterson and C. Zener, Geometric programming- Theory and application, John Wiley and Sons, Inc. NY, 1967.

[ I l l C. Eeightler and D. T. Phill$s, Applied geometric programming, John Wiley and Sons, Inc. NY, 1976.

1121 M. Avriel, (Edited) Advances in geometric programming, Plenum Press, NY, 1980.

Table.3: Comparison results of Proposed Model between 0.2Spm and 0 . 0 9 ~ technologies. .

l.lxlci 1 .~ . , ~ ~ , . ~ ~ - . ~ ~ ~ . . : ...I 2 2.2 2.4 2.6 2.8 3

W P .

Figure I Comparison of proposed model with SPICE

Computer-aided Design and Testing /487

250 300% Symbol-SPICE I -Proposed

zoo ~ -150 ~

' 50: ~

0 250 500 750 1000

5 --,roo

o ! - - 50f f

Frequency (MHz)

1 5 ~ 1

Symbol-SPICE -Proposed

IUiMMHZ I

,100 i 666MHz = I 500MHz 5 504 400MHz

333MHz i ZSOMHz

E

0 ;-- 0 100 ZOO 300 400

CL (fF)

Figure 2. Power-delay optimal PMOS sizes for different Figure 5. Power-delay optimal PMOS sizes for different input frequencies and different output load capacitances frequencies and different output load. (0.25-pm (0.25-pm technology) technology)

Symbol-SPICE -Proposed 100,

80 ! P i

0 250 500 750 1000

Frequency (MHz)

~~~ . .~ + Wp(250 MHz)!

1 - + Wp(333 MHz), - 5 1 -A- Wp(400 MHz), - X Wp(500 MHZ); i ;I +- Wp(666 MHz):

I -e- Wp(1000 MHZ) ~

0 1 i

6 Symbol-SPICE

5 4 1

1 1 ..... . . ~~~

0 200 400 600

CL (fF)

Figure 3. Power-delay optimal NMOS sizes for different frequencies and diff output load. (0.25-pm technology)

~i~~~~ 6, optimum PMOS siZe for ,,,in, p ~ p (predicted results using the proposed model for 0.09pm technology)

5 0 4 0

- 3 E 5 : ' 1

Symbol - SPICE

OOMHz

400MHz 333MHz Z50MHz

0 ' 0 1

0 100 200 300 400

CL (fv

3.5

3

2.5 - - 5 2 1

0.5

0

k W p ( 1 5 6 f F

-e-Wp(2dOfF

-+- Wp(250 f F + wp(300 f F + WP(3Mff) * WP(4W ff

.~ ~~ ~~~.

,. .. , ...l ~~~~ , 250 500 750 1000

Frequency (MHz)

Figure 4. Power-delay optimal NMOS sizes for different frequencies and diff output load. (0.25-tun technology)

Figure 7. Optimum PMOS Size for min. PDP (predicted results using the proposed model for 0.09pm technology)