8/12/2019 00500491

1/10

IDesign and Experimental Investigation of aThree-Phase High Power Density High EfficiencyJnity Power Factor PWM (VIENNA) Rectifier Employing aNovel Integrated Power Semiconductor Module

JOHANN. KOLAR,HANSERTL,RANZ. ZACHTechnical University Vienna, Power Electronics Section 359.5

Gusshausstrasse 27, Vienna A-1040,Austria/Europeemail: kolar@psl.iaee.tuwien.ac.at

Tel.: +43-1-58801-3833 Fax.: +43-1-505 88 70

ABSTRACTThe topic of this paper is the development of guidelines for the practical a pplication of a new power module (IXYS VUM25-E) realizing a bridge leg of athree-phase/switch/level PWM (VIENNA) rectifier system with low effectson the mains. The inner circuit s tructure of the power module is formed by abidirectional bipolar switch (realized by a power MOSFET connected acrossthe DC terminals of a diode bridge) and of two free-wheeling diodes. In afirst step the switching losses of the power MOSFET and of the freewheelingdiodes are determined by measurement in dependency on the switched cur-rent for characteristic values of the junction temperature. For connecting themodule to the passive components of the power circuit of the single-phasetest arrangement an appropriate designed power print minimizing the para-sitic lead inductances is applied. Furthermore, the isolated driving stage ofthe MOSFET is designed for minimum switching losses considering the oc-curring switching overvoltages and the ringing between the parasitic circuitelements. The cond uction losses of the semiconductor elements ar e calculateddirectly via simple analytical approximations of the mean and rms values (re-lated to a mains period) of the device currents. Based on the knowledge ofthe dependency of the main loss contributions of the semiconductors of thepower module on the operating parameters (mains voltage, output voltage,heat sink tempe rature and switching frequency) the thermall y maximum al-lowable mains current am plitude is calculated. Furthermore, for differentswitching frequencies an overview over the power loss contributions of theSemiconductor elements is given. Also, the reduction of the efficiency causedby the tota l semicond%tor losses is determined. Finally, the overall efficiencyof a PWM (VIENNA) rectifier system realized by using the IXYS VUM25-Emodule is estimated and further possible developments of this module arediscussed.

1 IntroductionDue to the effort (based on guidelines [I] ecommendations and regulations[2]) to limit the harmonic influence on the mains by power electronic sys-tems the development of converter concepts having low effects on the mainsbecomes increasingly importan t. In general one stri ves for

low circuit complexity and low component stresshigh power densityhigh efficiency* high reliability andcontrollability of the output voltage

besides obtaining a largely sinusoidal mains current shape (high power fac-tor and low THD). In the area of three-phase unidirectional A Cto -DC powerconversion these requirements can be met ideally by a three-phase/switch/levelPWM (VIENNA) rectifier system proposed in [3]. The basic structure of thepower circuit is shown in Fig.l(a). The adva ntages of the system are espe-cially

the purely sinusoidal shape of the m ains current (with the exception ofharmonics having switching frequency) being in phase with the mainsvoltage (i.e., resistive fundam ental mains be havior, high power factor);blocking voltage stress on the power semiconductors determined byonly half of the output voltage (for a system operating in the Euro-pean low voltage mains and for output voltages in the region U , =650.. ,750 V th e possibility of the applica tion of power MOSFETs with

0-7803-3044-7/965.00 1996 ~ E E E 514

a blocking voltage capability of UDSS 500V and, therefore, withlow on-resistance and low conduction losses is given; furthermore, lowswitching losses due to th e low switching voltage of the valves and possi-bility of realization of the uncontrolled valves as fast recovery epitaxialdiodes with a maximum blocking voltage URRM= 600V; the parasiticintrinsic free-wheeling diodes (characterized by a high reverse recoverytime) of the power MOSFE Ts are not used high switching frequencyand high power density of the system can be achieved;

IXYS WM2 5 E , I I -

(a)

Fig.1: Structure of the power circuit of a three-phase unidirectionalboost-type three-level PWM rectifier system according to [3] (cf. (a)).The combination of the power semiconductors of a bridge leg of the cir-cuit developed at the Technical University Vienna/Austria (short: VI-ENN A rectifier) has been offered since 01/1995 by IXYS Semicon-ductor GmbH as power modul IXYS VUM25-E. The prototyp ofthis module is shown in b), he interna l layout of the module is shownin (e) (dimensions of the ceramic base plate: 35" x 26") The char-acteristics of the valves of the module are identical to those of a boo$converter power module IXYS VUM24-05 as being used for single-phasepower factor correction. Accordingly, the nominal output power of a VI-ENNA rectifier consisting of three modules IXYS VUM25-E amountsto o % 16kW (dependent on the switching frequency); the nominalvalue of the output DC voltage has to be set typically to U 0 = 700V ifthe syst em is employed in th e Europe an low-voltage mains (line-to-linevoltage 400 Vrm).

8/12/2019 00500491

2/10

only one turn-off valve per phase (low control effort and high operat ingreliability); a short circuit of the ou tput vo ltage in the case of a controlerror of the power transistors canno t occur due to the circuit struct ure);low rated power of the inductances connected in series on the mainsside due to a three-level characteristic of the bridge legs (as comparedto conventional two-level bridge circuits the value of the inductance canbe reduced by about for equal harmonic level of the mains current andfor equal switching frequency); this leads to an increase of the systempower density and higher dynamic of the mains current control.

However, the circuit shows a relatively high assembly effort if a realizationwith discrete components is considered. This can be avioded to a large extentif the power semiconductors dies are contained in a power module.Based on this consideration, ABB-IXYS Semiconductor GmbH has developed(in cooperation with the Power Electronics Section of the Technical Univer-sity Vienna/Austria) the prototype of a power module shown in Fig.l(b)[4]. The basic thought has been to extend an already available single-phasePFC module (IXYS VUM24-05, cf. p. 86 in [5] or [SI) by adding of a powerdiode chip to the circuit s truc ture of a bridge leg of the three-phase circuitshown in Fig.l(a) . The inner structure of the module obtained thereby isshown in Fig.l(c). The semiconductor chips are identical with the elementsused in the discrete power semiconductor devices IXYS miniBLOC IXTN36N50 (power MOSFET, cf. p. 75 in [5]) and IXYS miniBLOCK DSEI2x30-06C (fast recovery epitaxial diode, cf. p. 28 in [7]). There, the powertransistor is realized by a parallel conncetion of two MOSFET chips takenfrom the same wafer. For avoiding an influence of the power circuit on thecontol circuit, the driving stage s of the power transistors has been separatedgeometrically clearly from the power terminals and a Kelvin-Source contacthas been provided (pin 7, cf. Fig.l(c )). For the package the outline knownfrom three-phase bridge rectifier modules (series IXYS VUO16NO1 or IXYSVU022N0 1, cf. p. 18 or p. 20 n [8]) has been selected (overall dimensions ofthe module: 63" x 31.6" x 17"). The power semiconductor chips areconnected by a high tempera ture soldering process with a copper layer beingapplied directly on a ceramic-oxide substrate (direct copper bonding (DCB)process, cf. [9]). There, the connection of the single elements is realized byappropriate structurization of the copper layer and via wire bonding. Theessential advantages of this construction are

high packaging densityminimization of parasitic lead inductanceshigh isolation voltagevery low thermal resistance of the ceramic substrate isolating the powersemiconductors from the heat sink and, therefore, low thermal resis-tance of the power semiconductors (obtained by low thickness of thesubs trate (0.63") and high thickness (300 pm) of the copper layer).

Furthermore, one has to point out the higher reliability of the module ascompared to assembling of discrete elements.Remark: If the bridge legs of the circuit according to Fig.1 ( a) are connectedin del ta, we receive a two-level PWM rectifier as introduced by W. Koczara in[lo]. However, in thi s case the module cannot be applied in the European lowvoltage mains due to the higher blocking voltage stress on the valves for two-level operation (the blocking voltage of the two-level converter is determinedby the total value of the output voltage).The topic of this paper is now to summarize the results of the first practicaltests of the power module an d to develop guidelines for an industrial a ppli-cation of the module based on the determined charac teris tic values of thepower semiconductors.In section 2 the switching losses of the power MOSFET and of a free-wheeling diodes of the module in dependency on the switched current forjunction temperatures of Tj = 25'C and 9 = llOC are determined. Forthe wiring of the semiconductor module with the passive components of thepower circuit of a testing arrangement (corresponding to a phase leg of athree-phase system) we use a carefully designed printed circuit board ( PCB)which minimizes the lead inductances. The current of the power switch isdetermined by using a shunt having high bandwidth. The turn-on and turn-off gate series resistors which essentially influence the switching losses areset with respect to the resulting switching overvoltages, the amplitude ofthe reverse recovery current and as much as possible) avoidance of ringingbetween parasitic circuit elements (e.g., between output capacitance of thepower transistor and lead inductances in connection with the inner induc-tance of the electrolyti c capacitors on the DC (ou tput) side). Based on theknowledge of the switching losses in dependency on the switched current the

mean switching loss within a mains period are calculated for an assumed si-nusoidal shape of t he switched current via simple analytical approximations.The calculation of the conduction losses of the power module is subject ofsection S. The forward characteri stic of the power diodes is approximatedthere by a current-independent forward voltage drop and a differential re-sistance. (The forward proper ties of the power MOSFET are characterizedby its on-state resistance ED+ .) For the loss-determining average and rmsvalues of the semiconductor currents analytical relationships are given whichare derived under consideration of the phase-symmetrical structure of thepower circuit and th e symmetry of the mains current system. If these ap-proximations are taken into account, the mean and rms values of all devicecurrents (and, therefore, the on-state losses of the semiconductor elements)can be calculated directly for given peak value of the mains current andgiven voltage transformation ratio of the system (ratio of output voltage tothe amplitude of the mains line-to-line voltage).In section 4 the relationships derived in section 3 are used for determiningthe maximum obtainab le mains current amplitude and three-phase power ofthe rectifier system (for given switching frequency and given maximum al-lowable junction temperature and heat sink temperature). The power losscontributions of the semiconductor elements of the module resulting for differ-ent switching frequencies are compiled. Also, the efficiency reduction causedby the semiconductor losses is determined. Therefore, for a practica l appli-cation of the module an essential support is given, especially concerning theselection of the switching frequency.Finally, in section 5 there is given an estimate of the overall efficiency of therectifier system to be expected and the possibilities of further developmentsof the module are discussed.

2 IXYS VUM25-E Switching EvaluationFor measuring the switching losses of the power semiconductors of the mod-ule we use the arrangement shown in Fig.2. Between positive output voltagebus and outpu t voltage center p oint a DC voltage ($Uo=350 V) is impressedhaving half of the nominal output voltage to be provided for a later real-ization. Between AC-side module input and positive output voltage bus aresistive-inductive load is inserted giving the test circuit the structure of abuck converter with free-wheeling diode D F + . By the circuit arrangementthe on-states and the commutation processes of the module within the pos-itive mains current half period are determined. When the power transisto ris in the on-state, we have a current flow via the mains side diode DN+,the transistor T and the center point diode DM+. ue to turning-off T theinput current of the module commutates into the free-wheeling diode DF+.Although the diodes DN+ nd DM+ articipate in conducting the current,they do not show any blocking voltage stress. The diodes DF-, N- ndDM- emain free of current.As section 2.4 shows, the t otal switching losses of the module are essentiallydetermined by the turn-on and turn-off losses of the power transistor. Asfurther switching loss contribu tions there occur forward-recovery losses andturn-off losses of DF+ or of DF- f the direction of the input current isreversed) and forward-recovery losses of DM+ or DM-).As already mentioned before, no blocking voltage results across DM+ n thecircuit according to Fig.2. T he reason for this is th at at turning-off of T theforward current becomes zero and no inverse current flow results which wouldremove the diffusion charge of the diode (an exception could be caused byoscillations between lead inductances and the output capacitance of T). Thestored electric charge is decreased by recombination. Therefore, there is nospecial requirement concerning the reverse-recovery behavior of the diodesDM+ nd DM-.A minimization of the switching losses of the power transistor can only beobtained by a switching speed as high as possible. In order to limit theswitching overvoltages occurring the re due to the high dildt- rate s we haveto provide as closely as possible a biplanar arrangement of commutatingcurrent paths which can be achieved, e.g., using a proper designed double-sided printed circuit board.For damping of the oscillations of the drain-source voltage of T following theturn-off process an RC-snubber is inser ted between the circuit nodes and2 (cf. Fig.2). (For negative input currents the RC-snubber would have tobe inserted between points 5 and 4.) The application of one RC-snubbereach for each current direction is required here because the prototype of themodule has only a Kelvin-source contact for the control of T. t does nothave a power source terminal. In the case tha t t he module would have an

515

8/12/2019 00500491

3/10

explicite source terminal an RC damping network could be inserted directlybetween drain and source of 2'. The dimensioning of the RC-snubber will betreated in section 2.2.We have to point ou t that wiring of the power circuit takes immediate in-fluence on the possible minimization of the switching losses. Therefore, thelayout of the printed circuit board used for measuring the switching losses(and the optimization of the gate drive) has to correspond already with thelayout of a bridge leg of the three-phase system which finally has to be real-ized. In order to obtain phase building blocks of equal structure we thereforehave decided to replace each output capacitor C+ or C-, respectively) by aparallel connection of three individual capacitors. Therefore, two indiv idualcapacitors (330pF/400V, one for the positive half leg and one for the nega-tive half leg) are allocated to each of the th ree phases. It is import ant to notethat no oscillations (due to the switching process) can occur between the par-allel capacitors. This is due to the relatively high parasitic equivalent seriesresistances of the electrolytic capacitors (RESR 0.15C2, LESLx 2 0 n H ) . Ifthe electrolytic capacitors would be conneted in parallel with foil capacitorsC, in order to improve the buffering action for high frequencies (cf. Fig.6 in[l l ])C, would have to be 2 in general (cf. e.g., p.166 in [13]). Due to the low capacity value CD here is no reduction of theturn-off overvoltage obtained, however. On the other hand, the energy lossin Ro remains limited to low values even for high switching frequency.For an isolated gate drive of the power MOSFET the IC combination UC3724/UC3725 of Unitrode Corp. is applied (cf. Fig.S). The realization of thedriver circuit is described in [14]. Therefore, a more detailed descriptioncan be omitted here. Wit h regard to low on-state losses of the MOSFET,U G S , ~ ~15V is chosen. For protection of the gate against voltage spikes azener diode (break-down voltage 16V) connected immediately at the controlterminals of the power module is applied.In order to make a arbitrary adjustment of the turn-on and turn-off speedof the power transistor possible, a complementary emitter follower is con-nected in series to the i ntegrated driver circuit. (Th e output current of thedriver IC UC3725 is limited t o

8/12/2019 00500491

4/10

Fig.3: Circuit diagram of the driver stage as usedfor measurement of the switching losses of the powermodule. The driver circuit requires a PCB area ofabout 5cm x 1.5cm if realized in conventional (non-SMD) technology.

safety margin of 40V remains for +Uo = 350V as compared to the drain-source break-down voltage of U D S S= 500V. With this, also for a transientunsymmetry of the part ial ou tput voltages a safe operat ion of the moduleis guaranteed. Furthermore, this makes possible to keep the a ctual blockingvoltage resulting a t th e MOSFET chip (which is higher than the voltage stressmeasured at the terminals of the module due to its inner wiring inductance)safely below U D S S .R G , ~ ~4.352 leads for il- = 50A and T,,j = T T , ~ 110C to a peakvalue I D ~ , R M 45A of the reverse recovery current of the freewheelingdiode. Then, for low turn-on losses the thermally maximum allowable peakcurrent stress of the transistor is not reached even for higher junction tem-peratures TD,,~. he experimental analysis shows that a reduction of RG,,,,,only marginally reduces the turn-on losses but the peak value of the reverserecovery current is still increased.Remark: As can be seen immediately from the structure of the power circuit(cf. Fig.l(a) ), for the VIENNA rectifier (contrary to two-level bridge circuits)no short circuit of the output voltages can occur for a control failure of thepower transisto r. Therefore, the overcurrent protec tion feature of the driverIC UC3725 is not applied here.

2.3 Current Measurement TechniqueDue to the system propagation delay (z 011s [IS]) of a clip-on ty pe cur rentprobe in combination with a current probe amplifier (Tektronix A6302 incombination with Tektronix AM503) being too high for an exact determina-tion of the switching power loss (cf. p. 1.702 in [17]) and due to the factthat an insertion of a current probe into the critical current path changes theinductance conditions and/or the switching overvoltages, the measurementof the transistor current is performed via a low-inductance shunt as proposedin [18] (cf. Fig.4). The shunt is realized by ten 1n-SMD resistors connectedin parallel. They are inserted into the current p ath which is realized in abiplanar fashion via a PCB with a copper layer on both sides connected atthe front end.As can be checked by calculation the change of the lead inductance of thecritical current pa th by the shunt is constrained to < 2nH. Therefore, it canbe neglected concerning measurement influences. The voltage drop of thecurrent to be measured is taken directly across the SMD esistors by a coaxialcable RG174 (characterist ic impedance 50 52) with a matched terminationin order to avoid reflections at the oscilloscope input. In connection withsituating the cable in a zone of the shunt with low magnetic field (cf. Fig.9in [ la]) the influence by an inductive voltage component is avoided therefore.The length of the coaxial cable is chosen such that a signal delay time resultswhich is identical to th e delay time occurring for measuring the voltage dropacross the shunt resistors by a voltage probe. By this a minimum error isguaranteed for the switching losses which are gained by multiplication oftransistor current and transistor voltage.A comparison measurement shows (with the exception of the signal delaymentioned before) an identical shape of the measurement signals for thecurrent measurement system Tektronix A6302/AM503 (bandwidth: DC-to-50 MHe) and for the low-inductance shunt (cf. Fig.5).

Remark: The shunt is not applicable for measurements over extended on-intervals of T due to th e generated heat caused by its high resistance (100 ma ).For measurement of the switching losses of the power module the temperaturerise of the shunt remains low due to the short pulse duration and the low re petition frequency of the considered on-off-on-off-cycles. Considering the verylow temperature coefficient of the used metal film SMD resistors the temper-ature error can be neglected therefore. An advantag e of the relatively highresistance value is the higher corner frequency of the frequency response ofthe shunt (according to W K = R R / L R )as compared to a low-resistance shuntof equal geometric design as would be applicable for continuous operation.

2.4 Switching BehaviorThe results of the measurements of the switching losses of the power MOS-FET of the module for = 350V, RG,,,,,= 4.352 and R G , ~ 1.252 arecompiled in Fig.6 . The losses are measured based on on-off-on-off-switchingcycles of short pulse duration and low repetition rate [19]. Due to the thenfollowing low junction temperature rise of the power semiconductors onlya small deviation of the junction temperature from the case and heat sinktemperature results. Therefore, the adjust ment of the junction temperature(which has to kept constant for a measurement series) can be achieved usinga proper pre-heating of the heat sink (cf. RH in Fig.2).The measurements have been carried out by using a digital storage oscillo-scope TEK TDS 5441 (500 MHz, 1Gs). For the voltage acquisition probesTEK P6139A (500MHz) have been used. It is important to point out that thevoltage measurement has to be done directly between drain and Kelvin-sourceof the power transi stor. (It must not be related t o the ground terminal of thelow-inductance shunt.) This can be explained by the fact th at for turning-onof T there results a transient voltage (which cannot be neglected) consist-ing of the forward-recovery voltage of D M + and the inductive voltage dropacross lead inductances inside the module. This transient voltage would leadto an apparent increase of the turn-on voltage of T and, therefore, also to anincrease of the measured turn-on loss. For the turn-off process the transistorvoltage woud be apparently reduced by an inductive voltage drop of oppositesign. Besides the measurement of too low turn-off power losses there wouldexist (e.g., during the course of optimizing the turn-on gate resistor R q on )the danger of exceeding the maximum admissible blocking voltage of thetransistor. The reason is, that due to the error in t he voltage measurementan appar ent safety margin to the blocking voltage limit would be pretended.As Fig.G(a) shows, the free-wheeling diodes DF of the power module showa pronounced soft-recovery behavior. In connection with the low-inductancewiring design of the power circuit therefore no turn-off overvoltage of thefreewheeling diode occurs.As a closer analysis shows and as can be checked for the power transistor byFig.G(e), the measured switching power losses of the power devices (powertransistor, free-wheeling diodes, center point diodes) can be expressed by alinear dependency

W p = k p Z N (1)on the switched current iN with good approximation. For the sum of turn-onand turn-off loss of the power transistor T there follows according to Fig.G(e)

t POWER PCBI M

517

Fig.4: Low-inductance shunt for measure-ment of the transistor current; (a): princi-ple of design; b): practical realization.

8/12/2019 00500491

5/10

Fig.5: Comparison of the current measurement system TEKA6302/AM503 and of the current acquisition by a low-inductivity shun t(cf. Fig.4) for the example of turn-off of the power transi stor. The cur-rent acquisition by the clipon current probe A6302 (cf. i ) shows adelay time Tt M 2511s being inadmissible high for an exact measurementof the switching power loss.

The switching losses of the free-wheeling diodes (sum of forward-recovery lossand turn-off power loss) can be described by

For d etermination of this characteristic value th e forward-recovery losses arecalculated based on the dat a sheet (cf. p. 29, Fig.6 in [7]); the turn-off lossesare determined based on the signal shapes measured for th e turn-on processof the power transistor.The switching losses of the center point diodes D M are caused exclusively bythe forward-recovery losses. There follows

Based on the characterization of the switching losses of the semiconductordevices according to Eq.(l) one can now as shown in more detail in thenext section) calculate in a simple way the switching losses of the elementsaveraged within the mains period.

3 Calculation of the Average Values of theSwitching Power Losses

If the power module is applied as bridge leg of a three-phase PWM rectifiersystem a sinusoidal variation of the switched current and, therefore, also ofthe switching power losses results over the mains period. Due to the thermalinert ia of the power semiconductors (cf. [5], p. 89, Fig.19) one can limit theconsideration to the average value of the switching power losses related toone mains period, however.

Fig.6: Analysis of the turn-on and turn-off behavior of the power transistor. (a)and b): turn-on and turn-off for T j = 25'C (refe rs to all semiconductor elementsof the module), representation of transistor current i~ (20A/div), transistor voltageUT (100V/div) and power loss p~ (25kW/div). ( c ) and d): as (a) and (b) butT j = llOC. e): dependency of transistor turn-on and turn-off energy loss on theswitched current and on the junction temperature T j current dependency of theturn-off energy shown by dashed lines. Time scale: 50 ns/div. Gate voltage levels:U,, = 0 , +15 V , emitter resistors of the driver stage: RG,~, , 4.3 Sa R G , ~1.2 Sa.The reduction of i~ during the rise of UT during turn-off is based on the effect ofthe RC dampin g network (inserted between nodes 5 and 2', cf. Fig.2) as turn-offsnubber. The reduction of UT during the rise of during turn-on shows the parasiticinductance L, of the critical current path (cf. Fig.2).

1 2

8

0.4

10 2 30 40 [ A 1 5 0IT

518

8/12/2019 00500491

6/10

For the calculation of simple analytical expressions of the average values ofthe the switching power losses of the semiconductor devices we assume (i)constant switching frequency f p and, (for the sake of concentrating on theessentials) (ii) a purely sinusoidal shape of the switched current (neglectionof the current ripple)

iN = N sin(9N) (PN = W N t . 2)Within a mains period one can now assign to each pulse interval a switchingloss energyof the respective considered device being dependent on the local value ~ N { P N } .Also,one can define a local switching power loss

WP = WP,off-on+ wP,on-off = k P i N { V } 3)1p p = - w p = w p f pTP (4)

The average value of the switching power loss related to a mains periodfollows therefore for the power transistor via

For the freewheeling diodes DF and the center point diodes DM we havedue to the limitation of the current flow to a mains half period

1 (6)D,P = g d kD,P iN{ (PN }fP d(PN .There, we have to insert for the factor k D,p (corresponding to a linear cu rrentdependency of the switching losses) the values k ~ ~ , pr k D x , p as given insection 2.4.3.1 Power TransistorBesides the power loss contribution defined by Eq.(5) (which can be deter-mined by measuring the external transistor current) we have to consider fora more detailed analys is also the power loss occurring for each turn-on prc-cess due to discharging the output capacitance Cos f the power MOSFET.For the voltage dependent capacitance we use - as a first approximation -the value valid for the nominal blocking voltage (CO,, M ln F, cf. [5], p.88, Fig.8). For the average value of the total switching losses of the powertransistor there follows then by considering of Eq.( 5

3.2 Power DiodesFor the average values of the switching power losses of the diodes DF andD M there follows under consideration of Eq.(6)

4 Calculation of the Average Values of theForward Losses

4.1 Forward Characteristics of the Power Semiconduc-tor Devices

4.1.1 Power DiodesThe forward characteristics of the power diodes as known rom the data sheet(cf. p. 88, Fig.10 in [5]) are approx imated according to

UD,F = uF,O + TDi D 9)by a current-independent forward voltage drop U , , in addition to a differ-ential resistance T D , In general, the average forward power loss of a powerdiode can be calculated then by

The forward characteristics of the diodes DM are described by UF,O= 1.25Vand TD = 10m n (related to TD,,~ 85OC, cf. section 6). For the diodes DNand Dp we set U F , O= 1.15V and TT = 10m n (related to T D , ~ 100C) dueto the current stress (being higher than for D M ) nd due to the then higherjunction temperature.

4.1.2 Power bansistorBasically one has to consider the dependency of the on-state resistance on th egate voltage, the junction te mperatu re and the magnitude of the drain currentfor calculati on of the conduction losses of a power MOSFET. The cur rentdependency of the on-state resistance is neglected on purpose for the sakeof simplifying the calculation. This is due to the fact that the overall lossesof the power transistor are essentially determined by the switching lossesas the considerations in section 6 show. The on- state characteristic of thepower transistor is described by a resistor R D ~ , ~ , { T ~ }hich is only depen denton the junction temperature due to the fixed gate voltage U G S , ~ ~15V.As reference value we set R D S , ~ ~ ~ , - , , . ~0.1223 (for IT = 25A). Thecorrection factor for the calculation of the actual resistance for a definedjunction temperature can be taken from the data sheet; e.g., we have for

I-

TT,j = llo'c

(cf. p. 88, Fig.5 in [5]).The average value of the forward power losses related to a mains periodfollows via

PT,F= I ~ , ~ , , , ~ R D S , ~ ~ { ~ ) (11)

4.2 Current Stresses of the Power Semiconductor De-vices of a Bridge LegIn the following the c urrent average and rms values are calculated as requiredfor the calculation of the on-state losses of the semiconductor elements ac-cording to section 4.1. Simple approximat ion formulas are derived whichcan be used beyond the scope of this paper for dimensioning of the powersemiconductors of a bridge leg of the VIENNA rectifier system. As alreadyassumed for the calcu lation of the switching losses (cf. section 3) we againassume

purely sinusoidal phase current shape andconstant switching frequency f p .

To this the assumption ofpurely resistive behavior of the mains voltage and current fu ndament ah(no phase displacement between mains voltage and the related mainscurrent)

is added. Furthermore, weneglect the mains frequency voltage drop across the AC side input in-ductances 1; (cf. Fig.l(a))

(this voltage drop shows typically a few percent of the mains voltage ampli-tude). For the simplest case the gating of the power transistor has to form alocal voltage average at the input of th e module

U0u U , ~ ~ ~ { ( P N I(1 Q T { ( P N I ) ~ u N{( P NI = N S ~ ~ ( P N (12)being equal to the related mains phase voltage. The time variation of therelative on-ti me CXTof the power transistor (essentially determining the for-ward losses of the module) can, therefore, be given directly for given outputvoltage independently of the amplitude of the mains phase current.Remark: Regarding the assumption of constant switching frequency we haveto point o ut t ha t (as a digital simulation shows) the approximations calcu-lated here are valid with high accurracy also for not constan t switching fre-quency (e.g., for hysteresis control of the ma ins current). Regarding the localaveraged (averaging within the pulse period) voltage at the i nput of the powermodule we want to point out th at th is voltage (dependent on the modulationmethod selected) also can obtain a non-sinusoidal shape. (A non-sinusoidal

519

8/12/2019 00500491

7/10

-

shape is present, e.g., for minimization of the mains current harmonics ofthe three-phase system via addition of zero-voltage components.) Accordingto the results of a checking calculation (which is omitted here for the sakeof brevity) this only influences essentially the local conduction losses. Theaverage values of the local conduction losses within a mains period remainlargely unchanged.For the sake of brevity in the following only basic considerations regardingthe derivations are discussed. The result ing character istic values of the semi-conductor cu rrents are compiled in Fig.7.

4.2.1 Diodes DN and D N -Dependent on the sign of the mains current only diode D N + or diode DN-takes part in conducting the current during the half fundamental (mains)period. The average and rms values of the diode curren t i ~ , herefore arecalculated via

4.2.2 Power Transistor TBased on the given time behavior of a T cf. Eq.(12)) there follow approd-mations of the transistor average and rms values via

The average value of the transistor current can be calculated alternativelyalso via using the node equations

(15)i .= { . iD,+ or+ for i~ > 0a D N - D,- for i N < 0(diode currents counted positive in forward direction) and

I ~ , a v g 2IN>avg 21Dp,avg . 16)The average value ID, a ~ g f the free-wheeling diode current required therewill be derived in section 4.2.4.4.2.3During the positive mains current half cycle the transistor current flows int he diode DM+, during t he negat ive mains current half cycle in t he diodeD M - to the output voltage center point. The average and rms values of thecenter point diode current follow therefore via

IDna,avg = i I T , a v g

Center Point Diodes DM+ and DAG

(17)1 1ID, , , , = JzIT.~- .4.2.4

If the reduction of the output power (caused by the losses) of the rectifieraverage valuepower balance

Free-Wheeling Diodes DF+ and DF-

of the free-wheeling diode current directly based on the

3 - - U0PN= -UNIN N I+,avgUo+ = Po2

Fig.7: Compil ation of the results of the analyt ical approx imat-ing calculation of mean an d rms values of the device currentsand of the averaged switchingpower losses (in dependency onthe mains current amplitude I N -and on the voltage transfor-mation ratio M = U o I f i i ? ~ ,U N : amplitude of the mainsphase voltage).

There, a timecons tant output voltage U , is assumed. Because a control ofthe potential of the output voltage center point suppresses the existance of anaverage value I M , ~ ~ ~0 of the center point cu rrent, the o utpu t power is onlydetermined by I+,avg This current average value is produced in equal partsby the single bridge legs due to the phase symmetry of the circuit struc tureand due to t he always same direction of the free-wheeling diode currents (ofthe phases) feeding the positive output voltage bus. Therefore we receive

For calculation of the rms value ID,,^,. we have to apply the node equationiD,+ = io,+ iT 20)

being valid for the positive mains current half cycle i N > 0. Furthermore,we have to consider tha t the freewheel ing diode D F , + and the transistor Tcarry the curren t flow always alternatively. Therefore, we have

i ~ , + i ~0 . ( 2 1 )From this there follows

(23)1or

I i N , r m s = I i p p m s + 5 G , r m arespectively. Thereby the rms value ID,,,,. of the free-wheeling current canbe given directly with consideration of Eqs.(13,14).

Mains Current Peak Value Allowable withRegard to TemperatureIn connection with a practical realization of a PWM rectifier system espe-dally t he obtainable maximum output power Po,,- (for a specific switchingfrequency fp and heat sink temperature T8) s of interest.According to Eq.(18) for fixed mains voltage amplitude the maximum rectifierpower is defined by the allowable maximum value IN,,- of the mains currentamplitude and, therefore, finally by the switching and conduction losses inconnection with the allowable thermal stress on the power semiconductors.For a calculation oft e have to set for each power semiconductor deviceof the module a maximum allowable value of the junction temperature ?,,=.With this, we have to determine the maximum allowable semiconductor loss

for a given heat sink temp erature T.. If one sets this power loss equal to thesum of the conduction and t he switching losses (known from section 3 andsection 4 in dependency on th e mains current amplitude)

pmax fi(iN,max} + pP(jN,,max] (25)then one can calculate directly the mains current amplitude i ~ , , , , ~or therespective considered device. The allowable stress on the module i thendefined by that semiconductor element which shows the lowest value IN,,- .As a comparison (which is not presented here in detail) of the thermal stresses

520

8/12/2019 00500491

8/10

5 I , I Ior a calculation O fN,- we have to set for each power semiconductor deviceof the module a maximum allowable value of t he junction temperatureWith this, we have to determine the maximum allowable semiconductor loss

for a given heat sink temperature T.. If one sets this power loss equal to thesum of the conduction and the switching losses (known from section 3 andsection 4 in dependency on the mains current amplitude)

p- = fi{fN,max}+ &'{fN,max} , (25)then one can calculate directly the mains current amplitude f~,- for therespective considered device. Th e allowable stress on the module if thendefined by that semiconductor element which shows the lowest value IN, .As a comparison (which is not presented here in detail) of the thermal stresseson the power semiconductor devices of the module shows (cf. Tab.l), inthe case at hand in the technically interesting switching frequency regionfp = 25 kHz.. . lo0 kHz the obtainable output power of the rectifier systemis limited by the value N,T,- which is related to the power transistor.Considering Eq.(7), *Eq .(l l), Pig.7, Eq.(24) and Eq.(25) there follows thecharacteristic value IN,,,,= = IN,T, for the allowable stress on he modulevia a solution of the quadratic equation

The operating conditions are described there by the heat sink temperatureT,,he maximum junction temperature T T J , ~ ~ ,he switching frequency f p ,the voltage transfer ratio M (cf. Fig.7) and the outp ut voltage UO.Based on Eq.(26) one can also, e.g., calculate in a simple manner the depen-dency of the thermally maximum allowable mains current amplitude or themaximum mains power on the heat sink temperature

IN - = IN,max{T.}fp,M,Uo,T,,,.. (27)(for fixed switching frequency fp, voltage transfer ratio M, output voltageU, and junction temperat ure In the same manner, this can be donefor the dependency of f ~ , ~ ~n the level of the mains voltage or on thevoltage transfer ratio

IN,max = IN,,~~{M}~P,UO,T,,,..,T. 28)(for fixed switching frequency, outpu t voltage, junction temperature and heatsink temperature).If one does not want to determine the mains current amplitude related to amaximum junction temperature but, vice versa, the junction temperature ofthe power transistor resulting for a given mains current amplitude we haveto extend Eq.(26) by analytical approximations of the temperature depen-dency of the turn-on resistance R D ~ , ~ ~nd of the factor kT,p determiningthe switching losses. For the sake of brevity, we have to omit a more detaileddiscussion of the calculation procedure.The results of an evaluation of Eq.(26) for the switching frequency regionfp = 25 kHz.. .l o0 kHz as nteresting for a practical realization of the recti-fier system) are shown in Fig.8. The calculations are based on the followingoperational parameters of the system a nd characteristic values of the powertransistor TT,j,max = lloocT. = 75'c ( & , m a = 92.1w)U0 = 700V

MRDS,~,,= 0.2240kT,p = 55

= 1.242 UN,, = 230V)CO,, = w 1 n F .

The value T T , ~ , ~ ~llOC (lying below the maximum allowable junct iontemperature ( T T , ~ , ~ ~125OC.. . 150'C) as given in the data sheet) is se-lected regarding a sufficient safety margin for the calculation which is basedon a multitude of approximations and with respect to a high operationalsafety of the rectifier system (cf. p. 282 in [15]). T he value T. = 75'Ccorresponds to a value being usual for dimensioning of an apparatus for amaximum ambient temperature in the region T. = 4OOC. . 5OoC.As Fig.8 shows, we have to reduce the mains current amplitude and, there-fore, the on-state power loss for maintaining the maximum allowable unction

[ I40

3

2

10

Fig.8: Dependency of the maximum allowable amplitude of themains current on the switching frequency f p for applicationof the power module.

temperature of the thermally critical power transistor for rising switching fre-quency and for rising switching loss. The curva ture of the characteristics canbe explained by th e quadrati c dependency of the on-state losses on the ampli-tude of the mains current (cf. Eq.(ll) and Fig.6). The linear increase of theswitching losses for rising switching frequency can, therefore, be compensatedby a less than linear decrease of the mains current amplitude.

6 Power Loss Break-Down of the ModuleIn order to give an overview over the losses resulting for the stationary ther-mally maximum allowable ampli tude of the mains current (and overthe there by given therm al utiliza tion of the different power semiconductorsof the module) Tab.1 shows the switching and conduction losses and thejunction temperatures of the semiconductor elements for characteristic val-ues of the switching frequency. Thereby, a heat sink temperatu re T. = 75OCis assumed. For th e therm al resistance of the power diodes according to theda ta sheet (cf. p. 87 in [5]) Rth,D,j-, = 1.8 6 is set there. Furthermore, inTab.1 the total power loss of the module

PM = PT + ~ ( P D NP D F + p D r ) (29)the efficiency reduction of the system

due to the power loss of the module and the mains power PN (being approx-imately equal t o the out put power) of the system are given.Based on a maximum allowable junct ion temperature of the power diodesbeing higher than T T ~ , ~ ~or equal operational safety the original assumptionis checked (cf. section 5), namely, th at the stationary maximum allowablemains current is determined by the power transistor.Remark: According to Tab.1 there exist junction temperatures T D ~ , ~z100C for the freewheeling diodes. The switching losses of the power transis-tor being determined essentially by the chip temperature of the freewheelingdiodes have been measured for T D , ~ llO C, however (cf. section 2.4).The factor kT P included in Eq.(26) (which almost exclusively determines th emaximum allowable mains current amplitude for higher switching frequency)therefore increases the safety margin of th e dimensioning. I n fact, therefore,for the calculated values IN,- we have to expect a junction temperature ofthe power transistor lying below T T , ~ , ~ ~ .According to Tab.1 we have for higher switching frequencies due to the highertransistor switching losses a lower value of the thermally maximum allowablemains current amplitude (or the obtainable mains power), and, therefore, alower utiliiat ion of the rate d power of the module. Due to the decreasingon-state losses of the diodes for decreasing mains current the total losses ofthe module drop witch increasing switching frequency (for constant junctiontemperature and power loss of the power transistor). However, the totallosses are still dominated by the transistor losses. Therefore, due to thelower mains power for higher swi tching frequency a higher efficiency reductionAqM results. If for realization of the rectifier system a high power density(and therefore a high switching frequency fp rz 100kHz) is required, we

521

8/12/2019 00500491

9/10

t A] 45 .2 34.2 26 .7 21.6PN [kW] 22 .1 16 .8 13.1 10.6

50 29 17 11PTF [wl 42 63 75 81TT,jT,p yc1wl 110 110 110 110P D ~ , FWI 21 15 11 8 .7TDNJ rc1PD,,F [WI 16 11 8 .2 6 . 4PD,,P [w] 2 .2 3 . 3 3 .8 4 .1TD , ,~C] 107 101 97 94PD - . F IW1 5 . 0 4 . 2 3.1 2.5-P ~ ~ , ~wj 0 . 7 1.1 1 .3 1 .4TDxa,j [cl 85 84 83 82pM,F LW 134 89 62 464 8 7 2 8 5 9 2pMpM [wlw l 182 161 147 138Aqh- [%I 2.5 2.9 3.4 3.9

Table 1: Power loss break-down of the semicon uctor module, maxi-mum allowable amplitude of the mains current IN,,= and obtainablemains power of the rectifier system PN ( U N , ~ ~2 3 0 V , heat sink tem-perature T. = 75C) in dependency on the switching frequency fp . PMdenotes the total loss of one module, A~)Mhe efficiency reduction of thethree-phase system caused by 3 PM.

have to tolerate a reduction of the efficiency of about 1% as compared tofp M 50 kHa for equal out put power) caused by semiconductor losses. Themaximum output power of the rectifier system is reduced by M 35 if theswitching frequency is increased from 50 kKz to 100 Ha.

7 Efficiency of the Rectifier System for Ap-plication of Power Module VUM25-E

Finally, we want to give an estimate for the total efficiency which can beexpected for application of the module (especially of interest for applicationof the rectifier system in a telecom power supply). Also, he distri bution ofthe losses to the components of the system shall be shown graphically. Forthe switching frequency we choose

fp = 5 0 k H ~with regard t o an always necessary compromise (for a practical realisation)between high utilization of the module (high outpu t power) and high effi-ciency on one side and high power density (high switching frequency) on theother side. With T ab.] there follows then for the maximum obtainable mainspower

P N , ~ , 16.8kW ( i ~34 .2A) .Besides the losses of the semiconductors of the module (already compiled inTab.1) we now have to consider for a loss break-down of the whole system

the resistive losses PL of the input inductances L, f the EM1 filter tobe provided on the mains side and of the wiring,the losses Pc of the capacitors C+ and C- buffering the DC outputvoltage,the power consumption PE of the gate driver stages, of the controlcircuit, electro-mechanical control elements (s tart-up relays etc.) and

* the power consumption pV of the cooling fans.The loss contribution PL s approximately represented by the assumption ofan equivalent loss resistor of about 80mn per phase (to be thought insertedinto the leads connecting to the mains), giving a tota l of

P , = 9 5 W .

The core losses of the input inductances L can be neglected in a first ap-proximation for the application of ferrite material. (In the case at hand a ninductance of L M 250pH per phase is required for achieving a mains currentripple of f 5 of the maximum mains current amplitude.)For the further loss contributions we set the values known from experience

P c = 1 5 WPE = 3 0 WPv = 40W

The total efficiency of the rectifier system

then follows asM 0 . 9 6 .r, PN,.,,..

8 ConclusionsIn this paper the switching losses and on-sta te losses of a new power modulefor realization of a bridge leg of a three-phase/switch/level PWM (VIENNA)rectifier are analyzed. Based on this the maximum output power of therectifier system is determined (which is limited by the junction temperatureof the power transistor) in dependency on the switching frequency. Also thepower loss break-down of the module is calculated and the efficiency of therectifier system is estimated.The considerations show tha t a system output power of M 16 kW with a totalefficiency of q M 96 can be achieved for a mains voltage of 400V,,. (line-to -h e) , a DC output voltage of 700 V , a heat sink temperature of T. = 75Cand an average switching frequency of fp = 50 kHz. The module thereforeis extremely well suited for the realization of sinusoidal current input stagesfor telecom power supply systems, for uninterruptable power supplies ( UPS) ,for battery chargers, electronic welding current sources or, in general, powersupplies for process technologies.Concerning the loss break-down of the rectifier system we have to summarizethat the total system losses for fp = 5OkHz (for maximum output power)are essentially determined by the power semiconductor losses ( A ~ M 3 ,cf. Fig.9). The main part of this loss contribution (M 8 ) is caused bythe transistor losses (switching losses M 40 , on-state losses M 18 ). As awhole the power loss of the module i s caused for fp = 50 kHz to about equalparts by switching-frequency-dependent (M 55 ) and switching-frequency-independent ( M 5 ) losses.If the switching frequency (e.g., regarding a higher power density of therectifier system) is increased to fp = 100kHz, this loss distribution is shiftednoticeable towards the switching losses, and, also, the relative losses of themodule are increased as a whole ( A ~ M 4 ) . The part of the switchingfrequency dependent losses amounts to % 6 6 , the part of the switching-frequency-independent losses to % 3 4 . The total losses are caused with apart of already 67 by the losses of the power transistors (switching lossesN 59 , on-state losses M 8 ). The dominance of the switching losses of thetransistors shows clearly the importance of minimizing the switching lossesvia optimizing the g ate drive of the power M O S F E T s and the optimizationof the layout of the P C B used for wiring the power components. An essential

PT F6 pTP2 PDF: DP PLI pc_I PE

50 100 150 2

Powe r Loss [wFig.9: Graphical representation of the loss contributions of the compc-nents of a rectifier system realized with the power module IXYS VUM25-E. Operating parameters: fp = 50 kHz, U N , ~ ~ ~230 V, U0 = 700 V,T. = 75C; Po M 16kW, 7 = 0.96.

522

8/12/2019 00500491

10/10

increase of the efficiency of the rectifier system can be obtained, however,by changing from hard-switching to soft-switching techniques, or by usageof non-dissipative (active) snubber c ircuits [ZO]. A (theoretica lly) completeavoidance of the switching losses would result for f p = 100kHz in an overallsystem efficiency (for maximum ou tpu t power) of 7 = 97.7% (A& w 1.3%).For practical realization a total efficiency of $5 97 seems to be achievable.Regarding possible further developments of the power module we want topoint out that (as Tab.1 shows clearly) the center point diodes DM have onlya low thermal utilization. For a new module generation one could consider,therefore, a reduction of the chip size of DM . The effect on the total powerloss of the module can be neglected in a first approximation, however. Amodification of the module should be considered also concerning the diodesD N . This diodes are presently realized using fast-recovery epitaxial devices;due to the operation principle of the VIENNA rectifier system they are notstressed with switching frequency blocking voltages. Therefore, they could bereplaced by conventional rectifier diodes resulting in a lower forward voltagedrop (lower on-state losses) and lower cost. This is also valid for the centerpoint diodes D M . For a simple way of designing a snubber for the powertransistor providing a power source terminal would be advantageous. Besidesusing a RC damping network in this case an over-voltage limiting elementcould be connected between drain and source of T. The power transistor isdesigned concerning the blocking voltage capability based on half the valueof the output voltage which is typically present for operation of the rectifiersystem in the European low-voltage mains. A limitation of the (stationary)blocking voltage of the power transistor has to be provided (in order to obtaina high operating safety) because, e.g., for a no-load condition the distributionof U, among the free-wheeling diodes Dp+ and D F - and the transistor T isonly defined by non-idealities of the devices (leakage currents). As opposed tothe blocking voltage stress of the diodes there is no direct limitation (causedby the circuit structure) of the blocking voltage of T to half of the outputvoltage given. Finally we have to mention however, that during the course ofextensive experimental tests of the module such a blocking voltage limitationhas been omitted. Despite this fact , no failure of the module has occurred.

ACKNOWLEDGEMENTThe authors would like to thank IXYS Semiconductor GmbH for the oppor-tunity to perform first experimental work on he pro totype of the novel powermodule IXYS VUM25-E and for the material support of the practical work.Substantial contributions of Dr.-Ing A. Lindemann of IXYS SemiconductorGmbH, Lampertheim, Germany, to the development of the power module arealso kindly appreciated.

References[l]Vereinigung Deutscher Elektrkitiitswerke Zentralverband

der elektrischen und elektronischen Industrie Deutschlands:Richtlinie fir den Anschlujl von pr im ir getakteten Schaltnetzteilen matE- 6 Drehstromeingang. VWEW-Verlag: Stresemannallee 30, D-6000Frankfurt am Main 70, 1.Ansgabe (1992).

[2] Key, T. S., and Ld, J. S.: Comparison of Standards and PowerSupply Design Options for Limiting Harmonic Distortion an Power Sys-tems. IEEE Transactions on Industry Applications, Vol. 29, No. 4, pp.688-695 (1993).

[3] Kolar, J. W., and Zach, F. C.: A Novel Three-phase Utility In-terface Minimizing Line Curren t Harmonics of High-Power Telecom-munications Rectifier Modules. Record of the 16 th IEEE InternationalTelecommunications Energy Conference, Vancouver, Canada, Oct. 30 -NOV. 3, pp. 367-374 (1994).

[4] Lindemann, A.: Investigations on Electromagnetic Compatibility ofPower semiconductor Modules Integration in a Converter. Proceedingsog the 13th International Power Conversion Conference, Niirnberg, Ger-many, June 20-22, pp. 251-262 (1995).

[5] IXYS Semiconductor GmbH: Standard Power MOSFET, Mega-MOSFET TM and MOSFET Modules. Products data booklet No. ),Publication D94011 DE, June 1994.[6] G r a b , D. R., and Schneider, T.: P F C Power Stage for BoostConverters (Part I Part II). PCIM Europe, P t. I: Vol. 4, No. 5, pp.

185-188, Pt . 11: Vol. 4, NO. 6, pp. 241-244 (1992).

[7] IXYS Semiconductor GmbH: Fast Recovery Epitazial Diodes(FRED). Product s da ta booklet, Publication D94012 DE, June 1994.

[8] IXYS Semiconductor GmbH: Single and Three-phase RectifierBridges. Prod ucts d ata booklet, Publication D94014 DE, June 1994.

[9] IXYS Semiconductor GmbH: Power Semiconductor Chips, DirectCopper Bonded (DCB) Ceramic Substrates. Pro ducts dat a booklet, Pub-lication D94018 DE, July 1994.

[lo] Koczara, W.: Unity Power Factor Three-phase Rectifier. Proceedingsof the 6th International (2nd European) Power Quality Conference, Mu-nich, Oct. 14-15, pp. 79-88 (1992).

[ l l ] Schmid, M.:Design and Analysis of a Compact High-Eficiency PWMConverter for Hybrid Vehicle. Proceedings of the Stockholm Power Tech(International Symposium on Electric Power Engineering), Stockholm,Sweden, June 18-22, Vol. Electrical Machines and Drives, pp. 268-273(1995).

[12] Maurice, B.: Environment Design Rules of Power MOSF ET inMedium Power Application. Proceedings of the 18th Power ConversionConference, Niirnberg, Germany, June 6-8, pp. 196-205 (1989).

[13] Peter, J. M.:Switching Behavior of Fast Diodes in Converter Circuits.Proceedings of the 8th Power Conversion International Conference, At-lantic City, NJ, April 2-5, pp. 152-168 (1984).

[14] O'Connor, J. A.: Unique Chip Pai r Simplifies Isolated High SideSwitch Drive. Unitrode Product and Applications Handbook 1993-94,Application Note U-127, pp. 91272-91287 (1993).

[15] Inniss. B.. and Carli. G.: A Novel 12kW Switch Mode Power SUDD~V..*Power Electronics Technology and Applications 1993, IEEE TechnologyUpdate Series (Editor: P. A. Thol lot) , New York: The Institu tion ofElectrical and Electronics Engineers, Inc., pp. 281-289 (1992).Tektronix, Inc.: AM 503s Current Probe System User Manual. (1992).Lembeye, Y., Keradec, J. P., and Lafore, D.: Measurement ofLosses ofFast Power Switches. Impact of Typical Causes of Inaccuracy.Proceedings ot the 6th European Conference on Power Electronics andApplications, Sevilla, Spa in, Sept. 19-21, Vol. 1,pp. 1.701-1.706 (1995).Ferreira, J.A., Cronje, W. A., and Relihan, W. A.: Integrationof High Frequency Current Shunts in Power Electronic Circuits. IEEETransactions on Power Electronics, Vol. 10, No. 1, pp. 32-37 (1995).Kolar, J.W., Ertl, H., Erhartt, L.L., and Zach, F. C.: Anal-ysis of the Turn-of f Behavior and Switching Losses of a 1200V/50AZero- Voltage or Zero-Current Switched IGBT. Proceeding of the IE EEIndustry Applications Society Annual Meeting, Dearborn, MI, Sept. 28

Oct. 4, Vol. 11 pp. 1508-1514 (1991).Vlatkovic, V., Borojevic, D., and Lee, F. C.: Soft-SwitchingThree-phase PWM Conversion Technology. Proceedings of the 12th An-nual Power Electronics Seminar, Blacksburg, VA, Sept. 11-13, pp. 17-22(1994).

523