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Synthesis of Current Mode Building Blocks for Fuzzy Logic Control Circuits

Marek J. Patyra and John E. Long

Department of Computer Engineering University of Minnesota, Duluth, MN 55812, USA

ABSTRACT Since the introduction of the first digital-based fuzzy logic controller chip [61 and [7], efficient hardware design of fuzzy logic control systems (FLCS) has drawn substantial attention 183. The interest in fuzzy logic hardware systems is motivated by the desperate need to provide fast fuzzy logic-based systems capable of operating in real time process control condi- tions. Fuzzy logic hardware implementation problems can be classi- fied into two basic cathegories: the digital approach and the analog approach.The digital approach was originated by Togai and Watanabe who developed the first digital fuzzy logic-based inference engine chip [6] and [7]. However, the digital approach to the fuzzy logic hardware implementation seems to be less efficient in contrast to analog, especially when the complexity and speed of a control problem are cru- cial. The transformation of a real-world fuzzy data into a binary format requires tremendous processing power that must be provided in the real time. Therefore, the analog solution offers a sufficient strategy to solve fuzzy logic control problems in dedicated hardware. Recently, successful implementation of current mode fuzzy logic controller developed in CMOS technology was reported [ 11, [21, and [31. This approach starts with the theoretic framework for fuzzy set operations that leads to the coherent representation of the fuzzy inference operations, including fuzzification and defuzzification. The proposed approach, uti- lizing the control strategy proposed by Mamdani, concen- trates on the algebraic correcmess and elegance. It is algebraically effective but it lacks the current mode circuit implementation insight. This drawback motivated the presented research. This paper presents a graph-oriented approach to the synthesis of fuzzy logic building blocks. The framework for synthesis of current-mode fuzzy logic circuits is derived and the graph representations of basic building blocks are developed. These blocks comprise the bounded difference circuit, the absolute difference circuit., the minimum circuit, the maximum circuit, and the membership function circuit. Thereafter, the circuit implementations are analyzed and the circuit implementation issues related to the accuracy of the fuzzy operations are discussed.

INTRODUCTION Using current representation of the fuzzy variable in fuzzy

logic operations is a natural and effective way of performing complex fuzzy inferencing like fuzzy based control, fuzzy reasoning etc. This direction of the fuzzy logic hardware implementation was originated by Yamakawa in mid 1980's [lo] and [ll]. He synthesized several current mode circuits that performed nine fuzzy logic operations (bounded difference, fuzzy complement, bounded product., fuzzy logic union, fuzzy logic intersection, bounded sum, implication, absolute difference, and fuzzy equivalence). It is interesting to mention that the bounded difference operator was used to express other eight fuzzy operations. Although he continued his research and development toward the mixed mode fuzzy logic circuits [4] and [9], the current mode approach stimu- lated many researchers to followed this way toward the on chip implementation of current mode fuzzy logic systems.

TERMINOLOGY Before we discuss the technical details of our approach, nec- essary terminology should be introduced. We use the empty circle to denote the current source terminal, usually single for the whole network. The current drain terminal is represented by the black circle. The current sourcing input terminal is denoted by an empty pentagon directed into the current flow, while the current sourcing output terminal is denoted by the same pentagon with the circle inside.

sourcing inpw draining output terminal terminal

Is1 J 1 ID0 -\

current drain terminal

J I I '/

swnming current source node terminal

sourcing ourpw draining inpur re&/ terminal

Figure 1 Transformation of the degenerated summing node.

The draining input terminal is denoted by a shaded pentagon, while the draining output terminal is denoted by a shaded pentagon with the circle inside. Generally, the summing node is denoted by the circle with a plus sign inside. The summing node can be created by any combination of draining and sourcing terminals. The degenerated summing node is just the connection of two nodes

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sourcing-output with draining-input or sourcing-input with draining-output. As an example of the introduced terminology consider the case of degenerated summing node shown in Fig- ure 1. In addition to illustrating each type of node and terminal, Fig- ure 1 also shows the transformation of the degenerated summing node into an ordinary branch. Observe that such a configuration does not limit the current in any branch as long as the proper directions of the currents are maintained. An output terminal forces the same current to flow into the input terminal. Moreover, the network composed of current source terminal, current drain terminal and collections of degenerated summing nodes with branches attached to them is trivial and currents in all branches are the same.

Figure 2 Two basic configurations of simplest ordinary summing node

Current processing may be achieved by the utilization of the ordinary summing nodes. Let us analyze the simplest, three- branch summing node. The important factor determining the characteristics of current processing is the type of the node as illustrated in Figure 2. These configurations were obtained by introducing an addi- tional terminal to the degenerated summing node connections shown in Figure 1. By this simple extension the real current processing node is obtained. In fact, if we consider the configuration shown in Figure l(a), we have: for I x X y , the current to flow in the sourcing input terminal is equal to (1x4~)~. If the opposite is handled (Ix

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MAX= X+ Y Qx=Y+ x @Y (2) The transformation from the graph represented BD to the graph represented MAX operator is then straightforward. By adding the summing node with the output sourcin&draining terminal representing variable X to the graph of the BD operator the graph of MAX is obtained. Again, two basic versions are illustrated in Figure 4. In a manner similar to the BD operator graph, there can be created eight configurations for MAX operator graph. Because of the lack of space they are omitted in this summary. Sym- bolically they can be coded as (1x0, Iyo), (1x1, IYO), (1x0, In), (1x1, I-) for MAXD and the Same set is valid for M A X , . An analogous approach applied to the union operator leads to two basic graph configurations illustrated in Figure 5 .

Figure 5 Two basic configurations of the graph representing MIN operator.

These configurations are developed based on the formula: MN=X QY QX=Y OX QY (3)

MEMBERSHIP FUNCTION CONFIGURATION Without going into implementation details of other basic fuzzy logic operators, we need to discuss one of the most important element of fuzzy logic processing: the membership function generator. Each fuzzy based inference process requires the generation of the membership function according to the fuzzy variable which should be represented in the rule evaluation. Therefore, we consider the membership function defined as follows:

As can be seen from (4), the definition involves the bounded difference of the unity value, which is the maximum available value for the defined universe of discourse and the absolute difference (AD) of variables X and Y. It is however straightforward to implement the graph of AD operator by means of two graphs representing BD operators. Keeping that in mind, two basic configurations for MBF' could be derived as illustrated in Figure 6. Modifying the current directions, eight versions of this graph can be obtained. In the implementations of MBF' shown in Figure 6, the most interesting element is the four terminal summing node, which provides a way to obtain the absolute difference and summation. As a result, the triangular member-

MBF' = IIO(XQY B Y ~ X ) (4)

ship function can be obtained with respect to variable x (represented by current Ix) with the variable Y (represented by current Iy) setting the central value of the triangle. There are more interesting implementations of membership function graph based on the following equations:

MBF2=MDJ{12, 11 @AD(XQY) (5)

MB@=MAX/l@ MDJ{I~ , I I e A D ( X Q Y J I (6) The first equation (5) represents the membership function of the trapezoidal form with the top level set at 12, and the second one (6) provides the low level shift by the value of &. As proved by Yamakawa [lo], other fuzzy logic operators, namely complement, bounded product, bounded sum, implication, and equivalence could be expressed by means of the bounded difference operator. Hence, each operator can be easily synthesized using the proposed graph approach. According to our previous study, the symmerric difference, algebraic difference, drastic sum, and drastic product can also be synthesized in this way.

Figure 6 Two basic configurations representing graph of the membership function.

IMPLEMENTATION ISSUES

Let us now discuss implementational issues behind the graph representation of fuzzy logic operations. As we mentioned earlier, the current mode fuzzy logic circuits may provide the attractive solutions [5 ] . In this case, all fuzzy variables are represented by appropriate currents and the graph of fuzzy operator or more sophisticated network reduces to the issues of the application of appropriate terminals. For sake of gen- erality we do not specify the technological details of the circuit implementations. It could be NMOS, BJT, CMOS, or BiCMOS technology. Having set the implementational issues which are schematically illustrated in Figure 7, it is clear that each graph has its counterpart in real electrical circuits. Regardless of the implementation of the current mirror, terminals match perfectly with the current mirror electrical characteristics in terms of the value and direction of the cur-

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rent flow.

Figure 7 Graph transformation into an n and p current mirrors.

With regard to implementation, we chose a CMOS technology for verification of the proposed approach. Using the M- Lsim tools from Mentor Graphics GDT Designer [12] mod- els of circuits corresponding to the discussed graphs were built and simulated. We simulated two versions of the eight circuitsrepresenting theBD graph. The first version was built of a simple ncurrent mirror and cascode p-current mirror, and the second was built of cascode ncurrent mirror and simple p-current mirror.

0 2.OE-8 4.E-8 6.E-8 8DE-8 1DE-7 Time [SI

Figure 8 Results of simulations o three embershi function

As we observed, the graph implementation involving simple n-current mirror and the cascode p-current mirror provides superior current repeatability. As a result, the development of the discussed fuzzy logic operators was done based on the simple n-current mirror and the cascode p-current mirror implementation of the appropriate graphs. We built and simulated three membership function circuits using the graph synthesis method presented in this paper. The corresponding graphs were based on equations (4), (9, and (6). The results are shown in Figure 8. The solid lines represent the ideal (expected) characteristics of MBF, MBF, and MBF3. As can be verified, the accuracy of the simulated circuits is moderate (up to 20% relative error), especially for the small currents (less than lo@.). This is primarily due to the inaccuracy of the simulator. In reality, better accuracy is expected. Not withstanding that inconvenience, the presented approach provides a fast method of synthesis and simulation of current mode fuzzy logic circuits.

circuits corresponding to MBF I P , MBF , and M B 8 graphs.

CONCLUDING REMARKS

and summation operators. As practice shows, it is the most common case for real implementations of fuzzy logic circuits. The proposed approach is reliable in terms of realiz- ability of such functions. It can be also proved that this approach is optimal in terms of the number of elements needed to synthesize the given operator/function. The graph approach offers also a wide flexibility in terms of the creation of sophisticated fuzzy logic functions, including control functions. Developing various versions for each operator is beneficial because it allows one to combine them together in the most optimal (minimal) configuration using the nodebranch reduction scheme presented earlier.

REFERENCES [l] L.Lemaitre. M. Patyra, and D. Mlynek. CMOS Fuzzy Logic

Controller in Current Mode, Proceedings of the IEEE CICC93, San Diego, CA, May 1993.

[2] L. Lemaitre, M. Patyra, and D. Mlynek, Integrated CMOS Fuzzy Logic Functions: A Current Mirror Based Approach, Proceedings of the IEEE ISCAS93, Chicago, IL, May 1993.

[3] L. Lemaitre, M. Patyra, and D. Mlynek, Fuzzy Logic Function Synthesis: A CMOS Current-Mode Solution, Proceedings of the 5th World IFSA Congress, Seoul, Korea, June 1993.

[4] T. Miki, H. Matsumoto. K. Ohto, and T. Yamakawa, Silicon Implementation for a Novel High-speed Fuzzy Inference Engine: Mega-Flips Analog Fuzzy Processor, Journal of Intelligent and Fuzzy Systems, vol. 1, no. 1, pp. 27-42, 1993.

[SI M.J. Patyra, VU1 Implementation of Fuzzy-Logic Circuits, Proceedings of the 4th World IFSA Congress, Brussels, Bel- gium, June 1991.

[6] M. Togai, H.Watanabe, Expert System on a Chip: An Engine for Real-Time Approximate Reasoning, IEEE Expert, pp. 55- 62, Fall 1986.

[7] M. Togai and H. Watanabe, A VLSI Implementation of a Fuzzy-Inference Engine: Toward an Expert System on a Chip, Information Sciences, vol. 38, pp. 147-163, 1986.

[8] H. Watanabe, W. Dettloff, K. Yount, A V U 1 Fuzzy Logic Controller with Reconfigurable, Cascadable Architecture, IEEE Journal of Solid-state Circuits, vol. 25, pp. 376-381. 1990.

[9] T. Yamakawa, A Fuzzy Inference Engine in Nonlinear Ana- log Mode and its Application to a Fuzzy Logic Control, IEEE Transactions on Neural Networks, vol. 4, no. 3. pp. 496-522, May 1993.

[lo] T. Yamakawa and T. Miki, The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Pro- cess, IEEE Transactions on Computers, vol. C-35, no. 2, pp. 161-167, February 1986.

[ 111 T. Yamakawa, T. Miki, and F. Ueno. The Design and Fabrica- tion of the Current Mode Fuzzy Logic Semi-custom IC in the Standard CMOS IC Technology, Proceedings of the 15th International Symposium on Multiple-Valued Logic, pp.

Summarizing, the presented framework features a homoge- nous, simple approach to the synthesis of fuzzy logic Opera- tors and functions if they are built of the bounded difference

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