INFORMATION SCIENCE 3RD SEM

10CS33 –LOGIC DESIGN

Author Details: Name: Praveena.MDesignation:APDepartment:ISE

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UNIT-3

Data Processing CircuitsObjectives

Write the truth table for exclusive-OR (EX-OR) Gates Explain the purpose of Parity Checking Design Parity Generators and Checkers Show how a Magnitude Comparator works Design of n-bit Magnitude Comparator Describe a diode ROM

IntroductionData-processing circuits are logic circuits that process binary data. Such circuits may be multiplexers,demultiplexers, encoder, decoder, EX-OR gates. First we consider multiplexers.

MultiplexerMultiplex means many into one. In digital computer networks, multiplexing is a method by which multiple digital data streams are combined into one signal over a shared medium. A digital circuit that performs the multiplexing of digital signals is called a multiplexer (or MUX in short). Multiplexer is a combinational logic circuit that can select one of many inputs. Multiplexer is also called a data selector. A simple 2-to-1 multiplexer block diagram and the switch equivalent circuit are as shown:

It has two inputs but only one output. By suitable control input or select input (sel) we can steer any input to the output.

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Design of 4-to-1 MultiplexerThe 4-to-1 multiplexer has four data inputs .To steer the four data inputs to the output

we need two. control inputs. The block diagram is as shown below:

The truth table describing the behavior of the 4-to-1 multiplexer:Control Inputs :OutputA B Y0 0 D00 1 D11 0 D21 1 D3The 74150The 74150 is a 16-to-1 TTL multiplexer disables It has active low output. It has a STROBE, an input signal that disables or enables the multiplexer.If STROBE= 0, MUX is enabledIf STROBE=1, MUX is disabled

EXAMPLE 1:Realize Y = A’B + B’C’ + ABC using 4--to-1 multiplexer.

Solution:We consider variables A and B as selector inputs in 4:1 mux & variable c in given as data input. Given logic equation Y = A’B + B’C’ + ABC in canonical form is Y= Σ m (0, 2, 3, 4, 7)is as shown.A B C Y0 0 0 10 0 1 00 1 0 10 1 1 11 0 0 11 0 1 0LD 10CS33

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20141 1 0 01 1 1 1

Considering C has MEV variable the truth table

A B C Y MEV O/P00

00

01

10

C’

00

11

01

11

1

11

00

01

10

C’

11

11

01

01

C

Comparing with equation of 4-to-1 multiplexer we seeD0 = C’D1 = 1D2 = C’D3 = C

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DemultiplexerDemultiplexer means one into many….One input and many outputs. By applying control signals, we can steer the input signal to one of the

output lines. The block diagram of a simple 1-to-2 demultiplexer block diagram and its switch equivalent circuit is as shown below:

Consider the block diagram of the general demultiplexer as shown below:

It has one input signal, ‘m’ control input or select signals, and ‘n’ output signals (n <= 2m).

Design of 1-to-2 Demultiplexer

The truth table of 1-to-2 demultiplexer is as shown below:

Data input

Select input Outputs

D A Y0 Y1

0 0 0 0

1 0 1 0

0 1 0 0

1 1 0 1

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The output expressions are Y0 = D.A’ and Y1 = A.D and the logic circuit realization is as shown below:

Demultiplexer ICs

The popular demultiplexer TTL ICs are listed below. They can also be used as decoders.

IC No. DEMUX Type Decoder Type

74154 1-to-16 4-to-16

74138 1-to-8 3-to-8

74155 1-to-4 2-to-4

Pinout diagram

Example 1:

Realize 1-to-32 demultiplexer using two 1-to-16 demultiplexers

Solution:

1-to-32 demux has 5 select variables A, B,C, D, E. We use two units of 1-to-16 demultiplexers to obtain32 outputs. If A = 0, the top IC is chosen, and if A = 1, the bottom IC is chosen. Depending on value ofBCDE, data is directed to one of the outputs. The 1-to-32 demultiplexer is realized as shown below:

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DECODER:

Demultiplexer can be used as a decoder. The data input of the demultiplexer is always connected to logic 1. The decoder inputs are given to the control or select lines. The inputs are decoded by activating one of the output lines. 1-to-n demultiplexer converted in to 1-of-n decoder. Only one of the ‘n’ output lines will be high.

The block diagram of 1-of-n decoder is as shown below:

Z

1-of-16 Decoder IC

74154 IC can be used as 1-of-16 decoder. 1-of-16 decoder is also called 4 line-to-16 line decoder. The block diagram is as shown below:

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Decoder Applications

Decoders can be used in combination logic circuit design.

Example 1 :

Show how using a 3-to-8 decoder and multi-input OR gates following Boolean expressions can be realized simultaneously:

f1(A, B, C) = Σ m(0, 4, 6)

f2(A, B, C) = Σ m(0, 5)

f3(A, B, C) = Σ m(1, 2, 3, 7)

Solution:

f1 = Σ m(0, 4, 6) = m0 + m4 + m6

f2 = Σ m(0, 5) = m0 + m5

f3 = Σ m(1, 2, 3, 7) = m1 + m2 + m3 + m7

We use OR gates to add the minterms. The Boolean expressions are realized as shown below:

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Encoder

Encoding is the process of converting familiar numbers or symbols into some code format. An encoder is a digital circuit that receives digits (decimal, octal, etc.) or alphabets or special symbols and converts them into their respective binary codes. It has ‘n’ input lines, only one of which is active. The activeinput is converted to a coded binary output with ‘m’ bits. Basically it is a combinational logic circuit.

Encoder performs operation reverse to that of a decoder. The block diagram is as shown:

Programmable ROMsA programmable ROM (PROM) allows the user instead of the manufacturer to store

the data. MaskROM (MROM) is a type of ROM whose contents are programmed by the IC manufacturer.

Drawing a PROM logic circuitIt is cumbersome to draw large PROM circuit with all the diodes. An alternative, streamlined drawingprocedure for PROMs is used. The simplified diagram of PROM is as shown:

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Universal Logic SolutionPROM is an universal logic solution. The AND gates generate all the fundamental products and the usercan then OR these products as needed to generate any Boolean output.

Programmable Array LogicProgrammable Array Logic (PAL) is a programmable array of logic gates on a single chip. PAL is differentvfrom a PROM. It has a programmable AND array and a fixed OR array.

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