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新數位電子術科秘笈 ( 使用 VHDL/ Verilog-HDL) 作者 : 賈證主、王炳聰 參考資料 : 全華圖書 數位電子乙級術科秘笈 ( 使用 VHDL/Verilog-HDL). VHDL/Verilog-HDL 入門 (1/15). VHDL/Verilog-HDL 入門 (2/15). VHDL/Verilog-HDL 入門 (3/15). VHDL/Verilog-HDL 入門 (4/15). VHDL/Verilog-HDL 入門 (5/15). - PowerPoint PPT Presentation
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(VHDL/Verilog-HDL): : (VHDL/Verilog-HDL)
VHDL/Verilog-HDL(1/15)
VHDL/Verilog-HDL(2/15)
VHDL/Verilog-HDL(3/15)
VHDL/Verilog-HDL(4/15)
VHDL/Verilog-HDL(5/15)
VHDL/Verilog-HDL(6/15)
VHDL/Verilog-HDL(7/15)
VHDL/Verilog-HDL(8/15)
VHDL/Verilog-HDL(9/15)
VHDL/Verilog-HDL(10/15)
VHDL/Verilog-HDL(11/15)
VHDL/Verilog-HDL(12/15)
VHDL/Verilog-HDL(13/15)
VHDL/Verilog-HDL(14/15)
VHDL/Verilog-HDL(15/15)
Quartus IIUSB(1) USB-BlasterUSB BlasterUSB BlasterUSBUSB Blaster C:/quartus/drivers/usb-blasterCPLD3.3V
(2) USB PORT:Tools => ProgrammerNo HardwareHardware setupUSB-BlasterSelect Hardware CloseUSB
(3) PRINT PORT:Add HardwareAdd HardwareHardware typePortByteBlasterMVLPT1OK
(4) CPLDCPLDCPLDQuartus II ProgrammerProgrammer*.pofModeJTAGProgram/configurestart
( )
() (SW1)ONAC 110V (NL1)DC (NL2)() VR1 CK1 1. VR1 09 2. VR1 09 3. VR1 09 4. VR1 09 () VR2 CK2 1. 2. VR2 () (S1)4 0000(S1)0000
Layout -- 30 -- 30 -- 60CPLD -- CPLD -- 3LayoutCPLD4
Layout(1/5)(1)4123443
Layout(2/5)
Layout(3/5)113P1P22P2P3P4P6P8P10P12P14P16 CPLD I/OCPLD I/O
Layout(4/5)CPLD I/OCPLD I/O3CPLDI/OCPLD I/O
Layout(5/5)CPLD I/OGND(3) C10C11R10U10()3
Layout
CPLD
/(9())CPLD I/OP2 / CK1P3 / CLRP4 / CK2P6 / A(LSB)P8 / BP10 / CP12 / D(MSB)P14(LSB)P16(MSB)
module mux_scan4(clr,ck1,ck2,dcba,sel);
inputclr,ck1,ck2;output [3:0] dcba;output [1:0] sel;reg[3:0] dcba;reg[3:0] dig0,dig1,dig2,dig3;reg[3:0] cnt;
assign sel = cnt[3:2];always @(negedge ck2)begincnt=9)dig0
()
() (SW1)ONAC (NL1)DC (NL2) 1. (S1)OFF 00 2. 15Hz012v CLOCK IN() 1. 09 (1) (2) (S2)00 2. 1.99 START/STOP (S1)ON (1) 90 (2) 90 () ()-2.00 1. 2. NL3 () (START/STOP)(S1)
Layout(1)
**P17GND**P22
(2)CPLD I/OLayout
(3) Layout
Layout
CPLD
/ (24())CPLD I/OP21/(P6)P10/()P4/()P2/()P13/P14/P7/(MSB)P3/P5/P9/(LSB)P15/(3,7)P19/(2,6)P16/(1,5,9)P18/(0,4,8)P6/P20/P1/xtalPIN_43
()
() 1. S1 ON S2 OFF S3 OFF 2. (SW1)ONAC 110V DC () 1. 1Hz TTL 1Hz 2. (1) S2 (S2 ON)00 23 (2) S3 (S3 ON)00 59() 1. S1 OFF 2. S1 ON ()
Layout(1)
Layout(1)CPLD IO(RC)
(1)CPLD IO(RC)
Layout
CPLD
/ (24())CPLD I/OP19/ 60P21 / P5 / P22 / 1HzP1 / P7 / 60P2 / 5VP20 / P11 / (MSB)P12 / (LSB)P14 / (MSB)P15 / P16 / P17 / (LSB)P8 /60P4 / P6 / 60(D10) / (clr)
TTL*: http://www.chwa.com.tw/newciv/bookinfo.asp?b_no=06177007 5kb *:
1 4M/2(16)(15Hz) : assign fs=cnt[15]; always@(negedge xtal) begin cnt
TTL*: http://www.chwa.com.tw/newciv/bookinfo.asp?b_no=06177007*:
2Gate clock always@(negedge fs) begin b1c
TTLmodule elec_ck(clr,p20,p21,p19,p5,p7,p22,p6,p8,p4,hra,hrb,xtal); input clr,p20,p21,p19,p5,p7,p22,xtal;output p6,p8,p4;output [1:0] hra;output [3:0] hrb;reg [1:0] hra;reg [3:0] hrb;reg b1c,b2c,y1,y1c,y2,y3,y4;wire fs,a1,b1,a2,b2,a3,b3,a4,b4;reg [15:0] cnt;assign a1 = p19;assign b1 = p21 & p22;assign a2 = p7;assign b2 = p5 & p22;assign a3 = p22;assign b3 = 1'b0;assign a4 = p7;assign b4 = 1'b1;
assign fs=cnt[15];always@(negedge xtal)begin cnt