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US010352987B2
( 12 ) United States Patent Thomas , Jr .
( 10 ) Patent No . : US 10 , 352 , 987 B2 ( 45 ) Date of Patent : Jul . 16 , 2019
( 54 ) SOLID STATE SWITCH POWER EMULATOR ( 71 ) Applicant : U . S . Army Research Laboratory
ATTN : RDRL - LOC - I , Washington , DC ( US )
31 / 2849 ; GO1R 31 / 2851 ; GOIR 31 / 318575 ; GOIR 31 / 31926 ; GOIR
31 / 31905 ; GOIR 31 / 3271 ; GOIR 31 / 2608 See application file for complete search history .
References Cited U . S . PATENT DOCUMENTS
( 56 ) ( 72 ) Inventor : Richard L . Thomas , Jr . , Baltimore ,
MD ( US ) ( 73 ) Assignee : The United States of America as
represented by the Secretary of the Army , Washington , DC ( US )
( * ) Notice : Subject to any disclaimer , the term of this patent is extended or adjusted under 35 U . S . C . 154 ( b ) by 77 days .
( 21 ) Appl . No . : 15 / 615 , 861 ( 22 ) Filed : Jun . 7 , 2017 ( 65 ) Prior Publication Data
US 2017 / 0350941 A1 Dec . 7 , 2017
4 , 694 , 242 A * 9 / 1987 Peterson . . . . . . . . . . GO1R 31 / 31905 324 / 537
5 , 414 , 352 A * 5 / 1995 Tanase . . . . . . . . . . . . . . . GOIR 31 / 2851 324 / 73 . 1
7 , 560 , 947 B2 * 7 / 2009 Sartschev . . . . . . . . GO1R 31 / 31924 324 / 762 . 01
2002 / 0125904 A1 * 9 / 2002 Eldridge . . . . . . . . . . GO1R 31 / 31721 324 / 754 . 03
( Continued ) Primary Examiner — Adolf D Berhane Assistant Examiner — Shahzeb K Ahmad ( 74 ) Attorney , Agent , or Firm — Christos S . Kyriakou ( 57 ) ABSTRACT A solid state switch power emulator circuit , the circuit including a high voltage section including a high voltage power supply ( HVPS ) ; a high voltage capacitor ( HVC ) electronically connected to the HVPS in parallel ; a high voltage switch ( HVS ) electronically connected to the HVC and the HVPS in series ; and a high voltage load ( HVL ) electronically connected to the HVS in series ; a low voltage section including a low voltage power supply ( LVPS ) ; a low voltage capacitor ( LVC ) electronically connected to the LVPS in parallel ; a low voltage switch ( LVS ) electronically connected to the LVPS and the LVC in series ; a low voltage load ( LVL ) electronically connected to the LVS in series ; and a high voltage diode ( HVD ) electronically connected to the LVL in series , wherein voltage levels associated with the low voltage section are less than voltage levels associated with the high voltage section .
18 Claims , 11 Drawing Sheets
Related U . S . Application Data ( 60 ) Provisional application No . 62 / 346 , 721 , filed on Jun .
7 , 2016
( 51 ) Int . Ci . GOIR 31 / 26 ( 2014 . 01 ) GOIR 31 / 327 ( 2006 . 01 ) GOIR 31 / 319 ( 2006 . 01 )
( 52 ) U . S . CI . CPC . . . . . GOIR 31 / 2608 ( 2013 . 01 ) ; GOIR 31 / 3271
( 2013 . 01 ) ; GOIR 31 / 31926 ( 2013 . 01 ) ( 58 ) Field of Classification Search
CPC . . HO2M 2001 / 0003 ; HO2M 1 / 32 ; HO2M 1 / 36 ; HO2M 1 / 38 ; HO2M 3 / 156 ; GOIR
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( 56 ) References Cited U . S . PATENT DOCUMENTS
2013 Wong . . . . . . . . . . . . . . . . . . . . . e m . . . GO 1321510 2013 / 0069666 A1 * 3 / 2013 Wong GOIR 31 / 40 324 / 511
2015 / 0323590 A1 * 11 / 2015 Xu . . . . . . . . . . . . . . . GOIR 31 / 2886 324 / 762 . 02
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SOLID STATE SWITCH POWER EMULATOR DUT gate signal is triggered on . The DUT gate signal may be triggered off a fourth delay time after the HVS gate signal
CROSS REFERENCE TO RELATED is triggered on . APPLICATION An embodiment herein provides a solid state switch
5 power emulator circuit , the circuit comprising a high voltage This application claims the benefit of U . S . Provisional section comprising a high voltage power supply ( HVPS ) ; a
Patent Application No . 62 / 346 , 721 filed on Jun . 7 , 2016 , the high voltage capacitor ( HVC ) electronically connected to contents of which , in its entirety , is herein incorporated by the HVPS in parallel ; a high voltage switch ( HVS ) elec reference . tronically connected to the HVC and the HVPS in series ; and
10 a high voltage load ( HVL ) electronically connected to the GOVERNMENT INTEREST HVS in series ; a low voltage section comprising a low
voltage power supply ( LVPS ) ; a low voltage capacitor The embodiments herein may be manufactured , used , ( LVC ) electronically connected to the LVPS in parallel ; a
low voltage switch ( LVS ) electronically connected to the and / or licensed by or for the United States Government 15 LVPS and the LVC in series ; a low voltage load ( LVL ) without the payment of royalties thereon . electronically connected to the LVS in series ; and a high voltage diode ( HVD ) electronically connected to the LVL in BACKGROUND series , wherein the high voltage section and the low voltage section are electronically connected to each other and to a Technical Field 20 device under test ( DUT ) in parallel , wherein voltage levels associated with the low voltage section are less than voltage
The embodiments herein generally relate to electronic levels associated with the high voltage section , and wherein circuits , and more particularly to a switch power emulator the high voltage section and the low voltage section are circuit . configured to emulate an electrical power being switched
25 through the DUT . Description of the Related Art A LVS gate signal may be triggered on after a first delay time after a DUT gate signal is triggered on , and wherein the
High voltage silicon carbide insulated - gate bipolar tran - DUT gate signal may be triggered off a second delay time sistors ( IGBTs ) with ratings above 10 kV are becoming after the LVS gate signal is triggered off . A HVS gate signal suitable for use in continuous power applications . To verify 30 may be triggered off after a third delay time after the DUT these components for continuous power operation requires gate signal is triggered on , and wherein the DUT gate signal power supplies , capacitors , and loads which may become may be triggered off a fourth delay time after the HVS gate dangerous and expensive at these high power levels . It is signal is triggered on . The HVS gate signal may be triggered desirable to provide a safe environment for accurate testing off a fifth delay time before the LVS gate signal is triggered of the high voltage silicon carbide IGBTs . 35 on . The HVS gate signal may be triggered on a sixth delay
time before the DUT gate signal is triggered off . SUMMARY An embodiment herein provides a method for switching
an electrical power through a device under test ( DUT ) , the In view of the foregoing , an embodiment herein provides method comprising electronically connecting the DUT to a
a solid state switch power emulator circuit , the circuit 40 high voltage section of a circuit and to a low voltage section comprising a high voltage section comprising a high voltage of the circuit , wherein the high voltage section and the low power supply ( HVPS ) ; a high voltage capacitor ( HVC ) voltage section of the circuit are connected to each other and electronically connected to the HVPS in parallel ; a high to the DUT in parallel , wherein voltage levels associated voltage switch ( HVS ) electronically connected to the HVC with the low voltage section are less than voltage levels and the HVPS in series ; and a high voltage load ( HVL ) 45 associated with the high voltage section , and wherein the electronically connected to the HVS in series ; a low voltage high voltage section comprises a high voltage power supply section comprising a low voltage power supply ( LVPS ) ; a ( HVPS ) ; a high voltage capacitor ( HVC ) electronically low voltage capacitor ( LVC ) electronically connected to the connected to the HVPS in parallel ; a high voltage switch LVPS in parallel ; a low voltage switch ( LVS ) electronically ( HVS ) electronically connected to the HVC and the HVPS connected to the LVPS and the LVC in series ; a low voltage 50 in series ; and a high voltage load ( HVL ) electronically load ( LVL ) electronically connected to the LVS in series ; connected to the HVS in series . and a high voltage diode ( HVD ) electronically connected to The low voltage section may comprise a low voltage the LVL in series , wherein voltage levels associated with the power supply ( LVPS ) ; a low voltage capacitor ( LVC ) elec low voltage section are less than voltage levels associated tronically connected to the LVPS in parallel ; a low voltage with the high voltage section . 55 switch ( LVS ) electronically connected to the LVPS and the
The high voltage section may be electronically connected LVC in series ; a low voltage load ( LVL ) electronically to the low voltage section in parallel . The high voltage connected to the LVS in series , and a high voltage diode section and the low voltage section may be electronically ( HVD ) electronically connected to the LVL in series . connected to a device under test ( DUT ) in parallel , and The method may further comprise triggering a LVS gate wherein the high voltage section and the low voltage section 60 signal on , after a first delay time after a DUT gate signal is may be configured to emulate an electrical power being triggered on . The method may further comprise triggering switched through the DUT . A LVS gate signal may be the DUT gate signal off , a second delay time after the LVS triggered on after a first delay time after a DUT gate signal gate signal is triggered off . The method may further com is triggered on . prise triggering a HVS gate signal off , after a third delay
The DUT gate signal may be triggered off a second delay 65 time after the DUT gate signal is triggered on . The method time after the LVS gate signal is triggered off . A HVS gate may further comprise triggering the DUT gate signal off a signal may be triggered off after a third delay time after the fourth delay time after the HVS gate signal is triggered on .
US 10 , 352 , 987 B2
The method may further comprise triggering the HVS gate The embodiments herein provide circuits configured to signal off a fifth delay time before the LVS gate signal is run a device under test ( DUT ) under the same conditions as triggered on . The method may further comprise triggering a conventional setup , but supplying only the DUT loss the HVS gate signal on a sixth delay time before the DUT power therefore using much smaller power supplies , lower gate signal is triggered off . 5 energy capacitors , and a lower power load for a less expen
These and other aspects of the embodiments herein will sive and far safer testbed . be better appreciated and understood when considered in When evaluating a device for continuous power applica conjunction with the following description and the accom tions one may look at the switching loss and the conduction
loss to understand how it will respond in use . Compared to panying drawings . It should be understood , however , that the following descriptions , while indicating preferred ? 10 the power the device is delivering the power consumed by
the device in switching and conduction losses are minimal . embodiments and numerous specific details thereof , are But , however minimal the device losses are , they are impor given by way of illustration and not of limitation . Many tant for the determination of how efficient the device is and changes and modifications may be made within the scope of its expected lifetime . In some embodiments herein , by using the embodiments herein without departing from the spirit ? ! 15 a high voltage power supply ( HVS ) and a low voltage power thereof , and the embodiments herein include all such modi supply ( LVS ) , the DUT is subjected to the switching and fications . conduction losses it would see if it were in a typical high
power circuit . BRIEF DESCRIPTION OF THE DRAWINGS An embodiment herein provides a circuit that provides
20 power to cover the losses a solid state switch would see if it The embodiments herein will be better understood from were switching power through it . An embodiment herein
the following detailed description with reference to the uses two power supplies to produce a voltage and current drawings , in which : waveform to the DUT . The embodiments herein provide for
FIG . 1 illustrates a schematic diagram of a circuit to effective and greatly efficient long term power switching test emulate power being switched through the device under test 25 of new high voltage solid state devices . ( DUT ) according to an embodiment herein ; Referring now to the drawings , and more particularly to
FIG . 2 illustrates a diagram of a gate signal for the DUT FIGS . 1 through 11 , where similar reference characters ( GDUT ) according to an embodiment herein ; denote corresponding features consistently throughout the
FIG . 3 illustrates a diagram illustrating GDUT and a gate figures , there are shown preferred embodiments . signal for a low voltage switch ( GLVS ) according to an 30 FIG . 1 is a schematic diagram illustrating a solid state embodiment herein ; switch power emulator circuit 100 according to an embodi
FIG . 4 illustrates a diagram of a full gating sequence ment herein . The circuit 100 includes a high voltage section according to an embodiment herein ; 102 and a low voltage section 104 . In an embodiment herein ,
FIG . 5 illustrates a diagram of a current through the DUT the high voltage section 102 is connected in parallel to the is shown when the GDUT and GLVS are the only gates in 35 low voltage section 104 . operation according to an embodiment herein ; In an embodiment herein , the high voltage section 102
FIG . 6 illustrates a diagram of the DUT current when only includes a high voltage power supply ( HVPS ) 106 , high the GDUT and GHVS are operated according to an embodi - voltage capacitor ( HVC ) 108 , high voltage switch ( HVS ) ment herein ; 110 , and a high voltage load ( HVL ) 112 . The HVC 108 may
FIG . 7 illustrates a diagram of a combined DUT current 40 be connected to the HVPS 106 in parallel . The HVS 110 and ( DUTC ) according to an embodiment herein ; the HVL 112 may be connected in series to each other and
FIG . 8 illustrates a diagram of power emulator circuitry to the combination of the HVC 108 and the HVPS 106 . results according to an embodiment herein ; In an embodiment herein , the low voltage section 104
FIG . 9 illustrates a diagram of the power emulator as well includes a low voltage power supply ( LVPS ) 114 , low as the controller and DUT according to an embodiment 45 voltage capacitor ( LVC ) 116 , low voltage switch ( LVS ) 118 , herein ; low voltage load ( LVL ) 120 and high voltage diodes ( HVD )
FIG . 10 illustrates a diagram of the power emulator 122 . The LVC 116 may be connected in parallel to the LVPS circuitry results according to an embodiment herein ; and 114 . The LVS 118 , the LVL 120 , and the HVD 122 may be
FIG . 11 is a flowchart illustrating a method for switching connected to each other and to the combination of the LVC an electrical power through a DUT according to an embodi - 50 116 and the LVPS 114 , in series . ment herein . In an embodiment herein , the components of the solid
state switch power emulator circuit 100 are arranged in a DETAILED DESCRIPTION circuit as shown in FIG . 1 to emulate power being switched
through the device under test ( DUT ) 124 . The embodiments herein and the various features and 55 In an embodiment herein , the DUT 126 is triggered using
advantageous details thereof are explained more fully with a gate signal for DUT 124 , namely GDUT 130 electronically reference to the non - limiting embodiments that are illus - coupled to the DUT 126 . The LVS 118 may be triggered by trated in the accompanying drawings and detailed in the a gate signal for the LVS 118 , namely GLVS 126 electroni following description . Descriptions of well - known compo - cally coupled to the LVS 118 . The HVS 110 may be nents and processing techniques are omitted so as to not 60 triggered by a gate signal for the HVS 110 , namely GHVS unnecessarily obscure the embodiments herein . The 128 electronically coupled to the HVS 110 . examples used herein are intended merely to facilitate an In an embodiment herein , for proper operation , the three understanding of ways in which the embodiments herein switches HVS 110 , LVS 118 , and DUT 124 are triggered in may be practiced and to further enable those of skill in the a certain , predetermined sequence . In an embodiment art to practice the embodiments herein . Accordingly , the 65 herein , the three switches HVS 110 , LVS 118 , and DUT 124 examples should not be construed as limiting the scope of are triggered according to the sequence illustrated in FIG . 2 the embodiments herein . through FIG . 4 .
US 10 , 352 , 987 B2
FIG . 2 , with reference to FIG . 1 , is a diagram illustrating 7 , the currents illustrated in FIG . 5 and FIG . 6 are combined the gate signal for the DUT 124 ( GDUT 130 ) which pro - to produce the current though the DUT 124 , as illustrated in vides the switching frequency and duty cycle for which the FIG . 7 . DUT , according to an exemplary embodiment herein . FIG . In an embodiment herein , the circuit 100 is configured to 2 illustrates an exemplary GDUT 130 voltage versus time . 5 switch 1 . 1 kV , 2 A at 1 kHz through an insulated gate bipolar
In an embodiment herein , the gate signal for the LVS 118 transistor ( IGBT ) . ( GLVS 126 ) must be triggered on some delayed time after FIG . 8 , with reference to FIGS . 1 through 7 , is a diagram the GDUT 130 has been triggered on , and the GLVS 126 illustrating simulation results of the voltage and current of
the DUT 124 , according to an exemplary embodiment must be triggered off some delay time before the GDUT 130 10 herein . As illustrated in the example of FIG . 8 , approxi is triggered off . FIG . 3 , with reference to FIGS . 1 through 2 , illustrates the mately 1 . 1 kV is switched producing a current of 2 A in the
DUT 124 . The 2 A current is only sustained for approxi GLVS 126 and the GDUT 130 trigger voltages versus time mately 1 us from the DUT 124 being turned on and according to an exemplary embodiment herein . In the reintroduced 1 us before the DUT 124 is turned off to block example illustrated by FIG . 3 , there is a 1 us delay between a i us delay between 15 the 1 . 1 kV , according to an exemplary embodiment herein . the GDUT 130 trigger voltage coming on and then the GLVS FIG . 9 , with reference to FIGS . 1 through 8 , is a diagram 126 trigger voltage coming on , and a 1 us delay between the illustrating simulation results of the voltage and current of GLVS 126 trigger voltage going off and then the GDUT 130 the DUT 124 while the circuit 100 is running with the LVS trigger voltage going off . 118 activated and the LVPS 114 raised to produce approxi
In an embodiment herein , when only the LVS 118 and the 20 mately 1 A , according to an exemplary embodiment herein . DUT 124 switches are in operation , it allows an on state This gives a mismatched current waveform through the current to flow through the DUT 124 without the switching DUT 124 , as shown in the example illustrated in FIG . 9 . losses of the DUT 124 , because the DUT 124 is gated on FIG . 10 , with reference to FIGS . 1 through 9 , is a diagram before the LVS 118 can supply current and the LVS 118 illustrating simulation results of the voltage and current of interrupts the current before the DUT 124 is switched off 25 the DUT 124 , when the LVPS 114 is increased to produce which is referred to as soft switching herein . approximately 2 A during the on state of the DUT 124 . This
In an embodiment herein , the gate signal for the HVS 110 gives a matched current waveform through the DUT 124 , as ( GHVS 128 ) is an inverse of the GLVS 126 . This may allow shown in the example illustrated in FIG . 10 . high voltage to be present when the DUT 124 is off and also FIG . 11 , with reference to FIGS . 1 through 10 , is a
during the transition time when the DUT 124 is triggered on 30 on 30 flowchart illustrating a method 200 , according to an embodi and off . Since high voltage is present during the DUT 124 ment herein . The method 200 may electronically connect
( 202 ) a DUT 124 to a high voltage section 102 of a circuit transition time , it will allow the appropriate switching losses 100 , and to a low voltage section 104 of the circuit 100 ; for the DUT 124 to be obtained . trigger ( 204 ) a LVS gate signal ( GLVS 126 ) on , after a first FIG . 4 , with reference to FIGS . 1 through 3 , is a diagram 4 35 delay time after a DUT gate signal ( GDUT 130 ) is triggered illustrating a full gating sequence of the GHVS 128 , GLVS on ; trigger ( 206 ) the DUT gate signal ( GDUT 130 ) off , a 126 , and GDUT 130 , according to an exemplary embodi second delay time after the LVS gate signal ( GLVS 126 ) is ment herein . The gate signal of the HVS 110 ( GHVS 128 ) triggered off ; trigger ( 208 ) a HVS gate signal ( GHVS 128 ) may be a direct inverse of the gate signal of the LVS 118 off , after a third delay time after the DUT gate signal ( GDUT ( GLVS 126 ) . As illustrated in FIG . 4 , the GHVS 128 turns 40 130 ) is triggered on ; trigger ( 210 ) the DUT gate signal off with a time delay after when the GDUT 130 turns on , and ( GDUT 130 ) off , a fourth delay time after the HVS gate a time delay before the GLVS 126 turns on . The GHVS 128 signal ( GHVS 128 ) is triggered on ; trigger ( 212 ) the HVS turns on a time delay after the GLVS 126 turns off and a time gate signal ( GHVS 128 ) off , a fifth delay time before the delay before the GDUT 130 turns off . LVS gate signal ( GLVS 126 ) is triggered on ; and trigger
In an embodiment herein , the gating sequence will pro - 45 ( 214 ) the HVS gate signal ( GHVS 128 ) on , a sixth delay duce two sets of current waveforms that the circuit 100 time before the DUT gate signal ( GDUT 130 ) is triggered combines to provide the appropriate current through the off . DUT . When the GDUT 130 and the GLVS 126 are the only The embodiments herein solve the problem of costly gates in operation the current through the DUT 124 is the overhead of waste energy or the risk of other experimental same as the current through the LVS 118 . 50 components in device evaluation . The embodiments herein
FIG . 5 , with reference to FIGS . 1 through 4 , is a diagram alternate between a high voltage and low voltage power illustrating the current through the LVS 118 ( or through the supply to produce one waveform to evaluate the power DUT 124 ) , when the GDUT 130 and the GLVS 126 are the switch device . only gates in operation in the circuit 100 , according to an In the embodiments herein , high voltage devices and embodiment herein . This current waveform may be a soft 55 section of the circuit 100 are capable of handling higher switching profile of the DUT 124 , because there are no voltage levels than low voltage devices and section of the switching losses in the DUT 124 . circuit 100 . For example , HVC 108 , GHVS 128 , HVS 110 ,
FIG . 6 , with reference to FIGS . 1 through 5 , is a diagram and HVL 112 can operate at higher voltage levels than LVC illustrating the current provided through the HVS 110 if only 116 , GLVS 126 , LVS 118 , and LVL 120 , and the HVPS 106 the GDUT 130 and the GHVS 128 are operated . This 60 source can produce higher voltage output than LVPS 114 waveform may produce only the currents that are associated source . to the switching loss of the DUT 124 . In an exemplary embodiment herein , the HVC 108 ,
FIG . 7 , with reference to FIGS . 1 through 6 , is a diagram GHVS 128 , HVS 110 , HVL 112 devices and the high illustrating the current through the DUT 124 , the HVS 110 , voltage section 102 , can operate in voltage levels above 10 and the LVS 118 when the GDUT 130 , the GHVS 128 , and 65 kV , and the low voltage section 104 and the LVC 116 , GLVS the GLVS 126 are switched in the sequence as shown in FIG . 126 , LVS 118 , LVL 120 , HVD 122 , GDUT 130 , and DUT 4 , according to an embodiment herein . As illustrated in FIG . 124 can operate in voltage levels below 10 kV . In an
US 10 , 352 , 987 B2
30
exemplary embodiment herein , the HVPS 106 source can 4 . The circuit of claim 3 , wherein a HVS gate signal is produce signals with a voltage higher than 10 kV , and the triggered off after a third delay time after said DUT gate LVPS 114 source can produce output signal with a voltage signal is triggered on . lower than 10 kV . In the embodiments herein , the capacitors 5 . The circuit of claim 4 , wherein said DUT gate signal is HVC 108 , LVC 116 may have any capacitance value . In the 5 triggered off a fourth delay time after said HVS gate signal embodiments herein , the loads HVL 112 , and LVL 120 may is triggered on . have any impedance value . In the illustrated embodiments 6 . A solid state switch power emulator circuit , said circuit HVS 110 , LVS 118 and DUT 124 are shown as high and low comprising : voltage switches and metal - oxide - semiconductor field - effect a high voltage section comprising : transistor ( MOSFETs ) . However , should be understood by a high voltage power supply ( HVPS ) ; persons of skill in the art that HVS 110 , LVS 118 and DUT a high voltage capacitor ( HVC ) electronically con 124 can be any type of solid state switch . nected to said HVPS in parallel ;
The foregoing description of the specific embodiments a high voltage switch ( HVS ) electronically connected will so fully reveal the general nature of the embodiments 15 . to said HVC and said HVPS in series ; and herein that others can , by applying current knowledge , a high voltage load ( HVL ) electronically connected to readily modify and / or adapt for various applications such said HVS in series ; specific embodiments without departing from the generic a low voltage section comprising : concept , and , therefore , such adaptations and modifications a low voltage power supply ( LVPS ) ; should and are intended to be comprehended within the 20 a low voltage capacitor ( LVC ) electronically connected meaning and range of equivalents of the disclosed embodi to said LVPS in parallel ; ments . It is to be understood that the phraseology or termi a low voltage switch ( LVS ) electronically connected to nology employed herein is for the purpose of description and said LVPS and said LVC in series ; not of limitation . Therefore , while the embodiments herein a low voltage load ( LVL ) electronically connected to have been described in terms of preferred embodiments , 25 said LVS in series ; and those skilled in the art will recognize that the embodiments a high voltage diode ( HVD ) electronically connected to herein can be practiced with modification within the spirit said LVL in series , and scope of the appended claims . wherein said high voltage section and said low voltage
section are electronically connected to each other and What is claimed is : to a device under test ( DUT ) in parallel , wherein 1 . A solid state switch power emulator circuit , said circuit voltage levels associated with the low voltage section
comprising : are less than voltage levels associated with the high a high voltage section comprising : voltage section , and wherein said high voltage section
a high voltage power supply ( HVPS ) ; and said low voltage section are configured to emulate a high voltage capacitor ( HVC ) electronically con - 35 an electrical power being switched through said DUT .
nected to said HVPS in parallel ; 7 . The circuit of claim 6 , wherein a LVS gate signal is a high voltage switch ( HVS ) electronically connected triggered on after a first delay time after a DUT gate signal
to said HVC and said HVPS in series ; and is triggered on , and wherein said DUT gate signal is trig a high voltage load ( HVL ) electronically connected to gered off a second delay time after said LVS gate signal is
said HVS in series ; 40 triggered off . a low voltage section comprising : 8 . The circuit of claim 7 , wherein a HVS gate signal is
a low voltage power supply ( LVPS ) ; triggered off after a third delay time after said DUT gate a low voltage capacitor ( LVC ) electronically connected signal is triggered on , and wherein said DUT gate signal is
to said LVPS in parallel ; triggered off a fourth delay time after said HVS gate signal a low voltage switch ( LVS ) electronically connected to 45 is triggered on .
said LVPS and said LVC in series ; 9 . The circuit of claim 8 , wherein said HVS gate signal is a low voltage load ( LVL ) electronically connected to triggered off a fifth delay time before said LVS gate signal
said LVS in series ; and is triggered on . a high voltage diode ( HVD ) electronically connected to 10 . The circuit of claim 9 , wherein said HVS gate signal
said LVL in series , 50 is triggered on a sixth delay time before said DUT gate wherein voltage levels associated with the low voltage signal is triggered off .
section are less than voltage levels associated with the 11 . A method for switching an electrical power through a high voltage section device under test ( DUT ) , said method comprising :
wherein said high voltage section is electronically con electronically connecting said DUT to a high voltage nected to said low voltage section 55 section of a circuit and to a low voltage section of said
and further wherein said high voltage section and said low circuit , wherein said high voltage section and said low voltage section are electronically connected to a device voltage section of said circuit are connected to each under test ( DUT ) in parallel , and wherein said high other and to said DUT in parallel , wherein voltage voltage section and said low voltage section are con levels associated with the low voltage section are less figured to emulate an electrical power being switched 60 than voltage levels associated with the high voltage through said DUT . section , and wherein said high voltage section com
2 . The circuit of claim 1 , wherein a LVS gate signal is prising : triggered on after a first delay time after a DUT gate signal a high voltage power supply ( HVPS ) ; is triggered on . a high voltage capacitor ( HVC ) electronically con
3 . The circuit of claim 2 , wherein said DUT gate signal is 65 nected to said HVPS in parallel ; triggered off a second delay time after said LVS gate signal a high voltage switch ( HVS ) electronically connected is triggered off . to said HVC and said HVPS in series ; and
US 10 , 352 , 987 B2 10
a high voltage load ( HVL ) electronically connected to said HVS in series .
12 . The method of claim 11 , wherein said low voltage section comprising :
a low voltage power supply ( LVPS ) ; 5 a low voltage capacitor ( LVC ) electronically connected to
said LVPS in parallel ; a low voltage switch ( LVS ) electronically connected to
said LVPS and said LVC in series ; a low voltage load ( LVL ) electronically connected to said 10 LVS in series ; and
a high voltage diode ( HVD ) electronically connected to said LVL in series .
13 . The method of claim 12 , further comprising triggering a LVS gate signal on , after a first delay time after a DUT gate 15 signal is triggered on .
14 . The method of claim 13 , further comprising triggering said DUT gate signal off , a second delay time after said LVS gate signal is triggered off .
15 . The method of claim 14 , further comprising triggering 20 a HVS gate signal off , after a third delay time after said DUT gate signal is triggered on .
16 . The method of claim 15 , further comprising triggering said DUT gate signal off a fourth delay time after said HVS gate signal is triggered on .
17 . The method of claim 16 , further comprising triggering said HVS gate signal off a fifth delay time before said LVS gate signal is triggered on .
18 . A method of claim 17 , further comprising triggering said HVS gate signal on a sixth delay time before said DUT 30 gate signal is triggered off .
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