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Spartan-II High Volume Solutions Overview

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High PerformanceSystem Features

Software and Cores

Smallest Die SizeLowest Possible Cost

Low Cost Plastic PackagesStreamlined Testing

Xilinx Spartan Series FPGAs

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100,000 gates for $10Pricing for 250,000 units, end-2000, slowest speed, cheapest package

Spartan-II Expands the Spartan Series

Expands ASIC market coverage over Spartan-XL— 2-3X gates per I/O pin, 5X total gates— 2X gates per dollar— 2X I/O performance

Integrates more system functions— DLLs, FIFOs, translators, bus interfaces (PCI)

Fast, predictable routing performance and easy-to-use design flows

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40K

$10$10

Spartan-XL

Spartan-II

Syst

em G

ates

1998 1999 2000 2001

Spartan-III

30K

250K

100K

FIFOsFIFOs

PALsPALs

HDLCHDLC

UARTsUARTs

32-bit, 33-32-bit, 33-MHz PCIMHz PCI

PCI-MIPS PCI-MIPS BridgeBridge

64 Bit PCI64 Bit PCI

Reed Reed Solomon Solomon EncoderEncoder

ATM IMA ATM IMA Graphics Card

Office Networking

Set-Top Box

Embedded uP Apps

Video Line Video Line BufferBuffer

Cable ModemEthernet Ethernet

MACMAC

Pricing for 250,000 units, slowest speed, cheapest package, indicated timeframe

Higher Density Enables New Applications

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50 100 150 200 250

200K

175K

150K

125K

100K

75K

50K

25K

0

I/Os

System Gates

XCS30/XLXCS20/XL

XCS05/XL

XCS40/XL

ASICs & Spartan FPGAsGates vs. I/Os

XCS10/XL

Spartan-II FPGAs

Gate A

rrays

Spartan/XLXC2S15

XC2S30

XC2S50

XC2S100

XC2S150

XC2S200

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Reprogrammability is the Advantage

Advantages over ASICs

Time to Market advantage— First to market increases revenue yield

Time in Market advantage— Increases the revenue yield while in field

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Spartan-IISpartan-II Low Cost Low PowerDensity (15K to 200K)High Volume

Spartan-IISpartan-II Low Cost Low PowerDensity (15K to 200K)High Volume

Virtex-E High I/O Performance Density (50K to 3.2M) System integration

Virtex-E High I/O Performance Density (50K to 3.2M) System integration

Architecture

FPGA Focus Products CY00

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Spartan-II Product MatrixDevice XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200

System Gates 15K 30K 50K 100K 150K 200KLogic Cells 432 972 1,728 2,700 3,888 5,292Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344Block RAM Blocks 4 6 8 10 12 14DLLs 4 4 4 4 4 4I/O StandardsSupported

16 16 16 16 16 16

Max I/O 86 132 176 196 260 284Packages VQ100 VQ100

TQ144 TQ144 TQ144 TQ144

CS144 CS144

PQ208 PQ208 PQ208 PQ208 PQ208

FG256 FG256 FG256 FG256

FG456 FG456 FG456

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-5

-5

Spartan-XL Spartan-II

-4

Spee

d

Virtex

-6

-5

-6

-4

Spartan-II Speed Grades

Strategy— Fast enough for high volume

applications— Simplify speed grade

offering

Implementation— Spartan-II offers -5 & -6

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DLL

CL IOB

IOB

IOB

IOB

IOB

IOBIOB

IOB

DLL

DLL DLL

CLCL

CL

. . .

. . .. .

.

. . .

CLB CLB

CLB CLB

RAM

RAM

RAM

RAM

I/O Routing Ring

I/O Routing Ring

True Dual-PortTM

4K bit RAM

Clock managementMultiply clockDivide clock

De-skew clock

Chip to BackplanePCI 33MHz 3.3VPCI 33MHz 5.0VPCI 66MHz 3.3VGTL, GTL+, AGP

Chip to MemoryHSTL-I, HSTL-IIIHSTL-IVSSTL3-I, SSTL3-IISSTL2-I, SSTL2-IICTT

Chip to ChipLVTTL, LVCMOS

SelectI/OTM

Technology

Logic and Distributed RAM

Configurable Logic Block (CLB)Delay Locked Loop (DLL)

4Kx12Kx21Kx4512x8

256x16

Block Memory

Spartan-II Architecture

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2ns

2ns

2ns2ns

CLB Array

High Performance Routing

Routing delay depends primarily on distance— Direction independent— Device-size independent

Predictable for early design analysis

Critical for cores

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$10$10

1998 1999 2000

Spartan-XL

Spartan-II

Graphics Add-In Card

Office Networking

Set-Top Box

xDSL Modems

200 MHz Memory Continuum - Transparent Bandwidth

Cable Modems

Internet Devices

DSP CoefficientsSmall FIFOs

16x1

Distributed RAM

Large FIFOs Video Line BuffersCache Tag Memory

4Kx12Kx21Kx4512x8

256x16

Block RAM

SDRAMSGRAM

PB SRAMDDR SRAMZBT SRAMQDR SRAM

External RAM

Pricing for 250,000 units, slowest speed, cheapest package, indicated timeframe

Block RAM Enables New Applications

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RAMB4_S4_S16

WEBENBRSTB CLKBADDRB[7:0]DIB[15:0]

WEAENARSTA CLKAADDRA[9:0]DIA[3:0]

DOA[3:0]

DOB[15:0]

Spartan-IITrue Dual-Port

Block RAM

Port A

Port BW

R

W

R

W

RR

W Data Flow Spartan-II A to B YesB to A YesA to A YesB to B Yes

Spartan-II Block RAM

True dual-port static RAM - 4K bits— Independently configurable port data width

– 4K x 1; 2K x 2; 1K x 4; 512 x 8; 256 x 16 — Fast synchronous read and write

– 2.5ns clock-to-output with 1.0ns input address/data setup

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DLL1 DLL2

DLL3 DLL4

Deskewclockson chip

Manage up to 4system clocks

Deskewclocks

on board

CascadeDLLs

Generateclocks• multiply• divide• shift

Convertclocklevelsusing

SelectI/O

Delay Locked Loops lower memory and board costs

Spartan-II Clock Management

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Spartan-II SelectI/O3 Types of I/O Interfaces

SDRA

M

SSTL

GTL+

LVTTL

LVCMOSHSTL

SRAM

PCIChip to Memory

SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III,HSTL-IV, CTT

Chip to BackplanePCI33-5V, PCI33-3.3V, GTL, GTL+, AGP

Chip to ChipLVTTL, LVCMOS,5-volt tolerant

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I/O Standards SummaryType Chip to

ChipChip toBackplane

Chip to Memory

Key Standards LVTTL,LVCMOS

GTL, GTL+,AGP

HSTL I, III, IV SSTL2, SSTL3

Key Highlights Highervoltageswing

Low voltageswing

Low voltage swing,low power, lownoise200-400 MHz

Low voltage swing, lowpower, low noiseSSTL3 83-166 MHzSSTL2 166-333 MHz

Primary Usage Legacyinterface

Pentium CPU,backplanes

High speed SRAM,MIPS/ UltraSparc-II

Synchronous DRAMinterfaces (SDR & DDR)

Applications Glue logic,ASIC chipto chip

Datacom,Pentium, add-in cards

Line cards,graphics cards,digital cameras,modems

3-D graphics cards,plasma LCD displays,DTV interfaces,Set top boxes

Vendors Mostvendors

Intel, TI Micron, IDT,Cypress, MIPS,IBM, etc.

Micron, Samsung,Toshiba, Hyundai, NEC,Siemens, etc.

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I/O Performance Using SelectI/O & DLL Technology

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Spartan-II Core Support

BaseBLOX basic functions— Arithmetic (adders, counters, multipliers, etcetera)— Memory (single port, dual port, FIFO, etcetera)

AllianceCORE support— Microprocessor peripherals— Microcontrollers— Memory controllers (SDRAM)— Communications

– ATM, Ethernet, error correction (Reed-Solomon, Viterbi), telecom (HDLC), etc.

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Spartan-II PCI LogiCORE Solutions

PCI32/33— XC2S30/50/100/150-5 PQ208

– Pre-release version based on advance speed files

PCI64/33— XC2S100/150-6 FG456

New PCI back-end design - in development— PLX-like, including DMA, FIFOs, and interrupt control

PCI-X Support - under evaluation

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GTL+

5-volt tolerant I/O

SDRAM

QDR SRAMs

MIPS uP

2x CLKPC

I

PLL

$7.50

PCI Master/Target Controller

$15

SSTL-3 Translators

$4

FIFOsDualPorts

$7 $2$40

$6

GTL+Backplane

Drivers

HSTL Translators

$6

Spartan-II: System IntegrationPCI-MIPS System

Controller

SSTL3

Clock Mgmt - Board deskew

Memory

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DLLsDelay Locked

Loops

SelectI/OTechnology

MemoryDistributed + Block

External

100,000 Gatesfor $10

Reprogrammable ASIC Replacement!Pricing for 250,000 units, end-2000, slowest speed, cheapest package

Spartan-II: The Total Solution

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Reprogrammability at ASIC prices

Spartan-II Summary

Expand ASIC market coverage for Spartan Series— More gates per I/O and more gates per dollar— Higher density and performance— New features: Block RAM, DLL, SelectI/O technology

Optimized for low cost

Software support in 2.1i with latest service pack