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(NASA-CR-150321) DEVICE MODEL FOR FETSIM CIRCUIT SIMULATION PROGRAM An Early Domestic Dissemination Report (RCA Advanced Technology Labs.) 15 p UncI as

NASA CONTRACTOR REPORT

NASA CR-150321

C4 /33 14542

DEVICE MODEL FOR FETSIM CIRCUIT SIMULATION PROGRAM

By P. Ramondetta Advanced Technology Laboratories Government Systems Division RCA Camden, New Jersey 08102

March 1977

Prepared for

NASA-George C. Marshall Space Flight Center Marshall Space Flight Center, Alabama 3581 2

-, I

https://ntrs.nasa.gov/search.jsp?R=19790024294 2020-03-22T04:59:28+00:00Z

Section

I

n

m

Table

1

2

.TABLE OF CONTENTS:

INTRODUCnON 00. 0 · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FETSIM MOS MODEL · . . . . . . . . . . . . . . . . . . . . . . . . ..... . CONCLUSION 0 • 0 0 0 0 · . . . . . . . . . . . ....... ,. . . . . . . . . . ..

liST OF TABLES

MOS Model Constants 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . . . . . .. CMOS/SOS Device Parameters . . . . . . . . . . . . . . . . . . . . . . . ..

iii

Page

1

2

9

Page

4

7

Symbol

s

m

I

g

V

A

K

Hz

cm3

min

in.

mil

C

k

M

c

m

n

Symbol

PMOS

IC

MSFC

NASA

STANDARD ABBREVIA TIONS

second

meter

liter

gram

volt

ampere

kelvin

hertz

cubic centimeter

minute

inch

10-3 inch

Celsius

kilo, 103

mega, 106

centi, 10-2

milli, 10-3

micro, 10-6

nano, 10-9

Definition

NONSTANDARD ABBREVIATIONS

Definition

P-channel Metal Oxide Semiconductor

Integrated Cil'cuit

George C. Marshall Space Flight Center

National Aeronautics and Space Administration

iv

Symbol

LSI

LSIC

MSI

MSIC

SSI.

SSIC

CAD

FETSIM

MOS

CMOS

SOS

Symbol

VG

V T

VTn

VTp

VTH

VD

Vs VDS VSAT

IDS

fi>n, p

NONSTANDARD ABBREVIATIONS (Concluded)

Defini tion.

Large Scale Integration

Large Scale Integrated Circuit

Medium Scale Integration

Medium Scale Integrated Circuit

Small Scale Integration

Small Scale Integrated Circuit

Computer Aided Design

MOS circuit simulation computer program

Metal oxide semiconducto r

Complementary metal oxide semiconductor

Silicon on sapphire

LIST OF SYMBOLS

Definition

Gate voltage

Threshold voltage

Threshold voltage for n devices

Threshold voltage for p devices

Effective threshold voltage; this term accounts for the gating effect.

Drain voltage

Source voltage

Drain-to-source voltage

Saturation voltage

Drain-to-source current

A constant which is a function of the MOS fabrication process (n for NMOS devices; p for PMOS devices).

v

Symbol

Q

N D

Iln

IIp

MOVAn,p

W

L

R

P

n

Du

LIST OF SYMBOLS (Concluded)

Definition

Channel conductance of MOS devices (n for NMOS devices; p for PMOS devices).

Fermi potential of the substrate

Thickness of .gate oxide

Dielectric permittivity of gate oxide (silicon dioxide)

Charge on an electron

Dielectric permittivity of channel region (silicon)

Channel doping level concentration for n devices (acceptors)

Channel roping level concentration for p devices (donors)

Channel mobility of electrons

Channel mobility of holes

An empirically determined factor which accounts for the mobility variation as a function of gate voltage.

Effective channel width

. Effective channel length

An empirically calculated factor which accounts for the finite slope of the drain characteristics in the saturation region (n for NMOS devices; p for PMOS devices).

Electrical resistance

Refers to p-device type

Refe~s to n-device type

Lateral diffusion

Thiclmess of sapphire

Channel leakage

Poly-over-epi capacitance

Metal-over-poly capacitance

Breakdown voltage (measured between drain and source)

vi

Section I

INTRODUCTIQN

The information presentedin this report includes a description of the MOS transistor model used in the FETSIM analysis program. CMOS/SOS device parameters are included. Typical device mobilities are given as well as the empirically deterrnined constants necessary to model second-order effect conductance variations due to gate voltage and saturated dr8.in voltage.

1

Section II

FETSIM MOS MODEL

The MOS model used in the FETSIM circuit analysis program is based on a derivation following that of Ihantola. 1 By considering the doping level(s) of the ionized acceptors (or donors) in the substrate :material, several second-order physical effects are implicitly accounted for. These include the apparent decreased carrier mobility resulting from heavy substrate doping and the gating effect associated with stacked devices.

A linearized empirical approach2 is utilized as a means of handling the finite drain conductances in the saturation region. In addition, surface channel mobility modulation, as a function of gate voltage, is modeled along the lines proposed by Schrieffer. 3

The resulting four-terminal, MOS-device model is ideally suited for large-signal analysis and is directly applicable to either bulk MOS calculations or dielectrically isolated device (SOS) calculations.

Essentially the model divides MOS transistor operation into one of three possible cases.

CASE I:

Case I is the trivial case; here the magnitude of the gate voltage is 'below the effective threshold voltage necessary to cause transistor conduction. In this case the device current is zero • .

1. H. K. J. Thantola, "Design Theory of a Surface Field Effect Transistor, " Solid State Electron., vol •. 7, PP. 423-430, June 1964 • .

2. S.R. Hofstein, Field Effect Transistors, Ed. by J. T. Wallmark and H. Johnson, Prentice-Hall, Englewood Cliffs, New Jersey, 1966.

3. J.R. Schrieffer, "Effective Carrier Mobility in Surface-Space Charge Layers," PhYSical Review, February 1955.

2

CASE II: IVG I> IVT I 'VD 1<; IVSATI '

ID = K {2V DS(V as-V T) -

All SOS Devices or Bulk Devices when source and substra te common

Case II handles the special case of a conducting transistor with its source and substrate electrically connected. The expression for the channel current contains three, terms - the first two of which are those found in the generally accepted model of Sah. 4 The third term, (~/3)~n (Vns + 2~F)3/2, introduces the effect of the substrate doping level. (The expressions for tP, K, VTH' VSAT' and a can be found in Table 1). It is this term that accounts for the reduced effective mobijity associated with highly doped MOS substrates. The (1 + avOS) factor accounts for the finite slope of the drain char­acteristics in the saturation region. SOS devices are always handled with CASE I and CASE II.

CASE ill: I V GS I > I V TH I All Bulk devices where source and substrate are.!!Q! connected I VD I~I VSAT I

Ivs '~I VSAT I - (VD2-V

S2

) - (4/3)tP n [(Vn + 2tf>F?/2

(V S +2tPF

) 3/2} ) (1 + aV DS)

Note: V G' V D' & V S are measured relative to the substrate.

Case III covers the generalized and more complicated case where neither the source nor the drain is connected to the substrate. (When either the source or the drain is' connected to the substrate, Case III reduces to Case II.)

Case III permits the accurate handling of "stacked" transistors (for example, three input NOR gates)., Generall y, ,this case applies to bulk devices only. However, it is used in SOS calculations whenever device substrates are not permitted to "float" 0

The model is programmed i'n such a way as to set V D=V SA T whenever V D > V G -VTH, and Vs == VSAT whenever Vs ~V G - VTHo

4. C. T. Sah, "Characteristics of Metal-oxide-Semiconductor Transistors," rEEE Transactions on Electron Devices, July 1964, pp. 324-325.

3

Symbol

~n,p

K

~

VTH

a.n,p

VSAT

fJF

TABLE 1. MOS MODEL CONSTANTS

Value

T ox E ox

t2ESQNA,D

Pn Kn = 1 + MOVAn

(V G-V S-V T)

K . = ILp P 1 + MOVA <YG-V~-V rr)

p I

V T ± 9' n, p ~ V S + 2fJ F

Typical Values

a. = 0.01 n

a. = 0.02 P

E W ox

2T L ox

E W ox

2T L ox

-2~F { \p + (9,,;; +211F +VG - vTT (

N A,D ~ 0.026 log 10

1.45 x 10

Comments

A constant which is a function of the

MOS fabrication process.

The sign is "+" for enhancement mode

NMOS transistors. This term accounts

for the gating effect.

This is an empirically calculated

factor which accounts for the finite

s lope of the drain characteristics in

the saturation regiOn.

The Fermi potential of the substrate.

TABLE 1. MOS MODEL CONSTANTS (Continued)

Symbol Value Comments

Typical Value

MOVAn,p· 0.03 This is an empirically determined facto r, which accounts fo r the mobility variation as a function of gate voltage.

W, L Effective channel width and channel length.

Q 0.16 x 10-18 Charge on an electron, in coulombs.

C11

The programming technique permits saturated transistors and the gating effect to be handled.

MOS transistors processed in a bulk LsI technology share a common substrate. Generally NMOS devices are fabricated within a common,p-well while PMOS devices are fabricated within a common n-type material. Inherent in this scheme is the pos­sibility that the sources and drains of "stacked" transistors (in functional gates and transmission gates) can become back biased with respect to the fixed potential of the common substrates. This "gating effect" gives rise to an apparent increase in the threshold voltages of the associated transistors. This phenomenon is modeled in the equations of CASE Ill.

In comparison, MOS transistors processed in one of the SOS LSI technologies are fabricated within separate, independent islands of substrate material. This technique leaves the channel material free to be defined by the source or drain potentials of each transistor. In the case of NMOS devices, the p-type channel material is defined by the source or drain - whichever is at the lowe r potential. Similarly for PMOS de­vices, the n-type channel material is defined by the source or drain, whichever is the higher potential. This phenomenon is modeled by automatically defining the sub­strate of each SOS-LSI transistor to be at the lowest of the source or drain potentials for n-devices and highest of the source or drain potentials for p-devices. When this is done, the more generalized CASE m reduces to CASE n.

A nominal set of parameter values that is applicable for the current CMoslsos processes available at the RCA Solid State Technology Center is shown in Table 2. From the chatmel conductance values listed, typical mobility values can be calculated. For example,

K (2 T ) IJ. = n ......illL = 319 cm2/volt-second n E

ox

IJ. = 191 cm2/volt-second. p

Using the typical device parameters listed in Table 2, the FETSIM model calcu­lates saturated device currents (at '10 volts) of 1.2 and 0.8 mA for the n and p transistors, respectively. These currents are based on an assumed device width of 1. 0 mil. The mobilities used for the calculation are 319 and 191 cm2/volt-second for the n and p devices, respectively. In addition, the mobility modulation terms MOVA n, p were assumed to be O.

When it becomes necessary to model the effects of mobility variation as a function of gate voltage, the MOVA n , p terms must be chosen to match the observed mobility modulation phenomenon. . The empirical data will be a function of the particular

6

TABLE 2. CMOS/SOS DEVICE PARAMETERS

Parameter Symbol Units or

Min. Typical Max. Test Conditions

Threshold voltage VTn Vn=Va , ~ = 10 p.A 0.5 2.5

T = 25'C, w = 2.0 mils

Threshold voltage VTp VD=Va , ID = 10 p.A -0.5 -2.5

T = 25"C, w ,;, 2. 0 mils

Channel conductance p.E K K =~ AV2 (XIO-6) 5.0

n 2T ox

p. E ? 6 K K 2 T

OX AV· (X 10- ) 3.0

I p ox

Breakdown voltage BVDSP

In = 10p.A, Va = 0 V 20 23 I I BVDSn

In=-lOIlA, Va =0"1 -20 -30

Dielectric constant E 0.885 x 10-13 F/cm 3.9 3.9 I

ox . Oxide thickness T Channel A 1000 1100 1200

ox • T Field A 6000 7000 aooo

ox Channel length 1 As defined In mils 0.25

0.30

Lateral diffusion Du n

mils 0.03

Du mils 0.03 P

Sapphire thickness T mils 14 s

Metal-to-metal spacing mils 0.3

Metal-to-dlffused region spacing mils 0.1 . Metal thickness TAl A 10,000 .

Metal width mils 0.4 I

Diffused-reglon to diffused-region spacing mils 0.2

I N-epi doping (X 1015 cm-3) 2

P-epi doping (X 1015 em-3) 3 I I

N+ epi resistance R ohms/ square 85 i

P+ epi resistance R ohms/square 65

N+ poly resistance R ohms/square 200 j-

P+ poly resistance R ohms/square 70 \

! Channel leakage Iron VG = 0 nA/mll 10 25 i

Channel leakage I Va = 0 nA/mll 10 25 I DOp. I Body region tie Floating

I Poly-over-epi capacitance Cox pF/square 0.28 I Metal-over-poly capacitance C pF/square 0.076 ! mp

7

process under examination. Generally the MOVAntI> terms may be set equal to each other (MOVA n ;: MOVA p). Measured conductances for both the bulk and 50S tech­nologies suggest a typicril mobility reductlon of 20 percent over a lO-volt operating range. Specifically, the mobility at V G = 10 volts is reduced to 80 percent of its value measured at the onset of conductlon (V G =VT). To model this mobility variation, the MOVA terms should be set equal to 0.030 (MOVA n = MOVA p = 0.03). It is important to note, however, that whenever finite MOVA terms are introduced, the mobility terms used with the model must be artificially increased to guarantee co rrect scaling. For example, fixed electron mobilities of 319 cm2/volt-second would appear as 319 cm2/volt-second at V G = V T and as 246 cm2/volt-second at V G = 10 volts.

8

Section m

CONCLUSION

The FETSIM MOS transistor model has been described. The means by which this model handles both SOS and bulk transistor devices has been discussed. In addition, a complete set of typical processing and empirically derived model constants has also been provided.

9 .l}u.s. GOVERNMENT JtRINTING OFFICE 1977-740'()491108 REGION NO.4

TECHNICAL REPORT STANDARD TITLE PAGE 1. REPORT 'j('l. 3. RECIPIENT'S CATALOG NO.

/

2. GOVERNMENT ACCESSION NO.

NASA CR-i50::>2i ~.--~~-----~~~~-----------~---------------------------+--~---~~~-------------; II. TITLE ANI') SUBTrrLE 5. REPORT DATE

March 1977 Device Model for FETSIM Circuit Simulation Program 6. PERFORMING ORGANIZATION CODE

t---- --... ----.------------------------+:-::'=-==:-=::':-:":":':-:-:::==:7.':':-:;-;;-::.-;-;;--:;-;;:;;;:::-;;;;:;:;:~ .... '1'1110""'\ a.PERFORMING ORGANIZATION REPORr #

1 P. Hamondetta 10. WORK UNI~ NO.

11. CONTRACT OR GRANT NO.

NAS8-31325

9. PERFORMING ORGANIZATION NAME AND ADDRESS

Advanced Technology Laboratories Government Systems Division, RCA Camden, New Jersey 08102

~-------------------------------------------------------------; 13. TYPE OF REPOR",' 8: PER 100 COVERED

12. SPONSORING AGENCY NAME AND ADDRESS

National Aeronautics and Space Administration Washington, D. C. 20546

15. SUPPLEMENTARY NOTES

II. ABSTRACT

Contractor Report

14. SPONSORING AGENCY CODE

The information presented in this report includes a description of the MOS transistor used in the FETSIM analysis program. CMOS/SOS device parameters are included. Typical device mobilities are given as well as the empirically determined constants necessary to model second-order effect conductance variations due to gate voltage and saturated drain voltage. i

;

17. KE'I WORDS

~~~~~~~~~~~~~~----~~~~~~~~~~L~~~--____ - __ 19. SECURITY CLASSIF. (of thl. r.pcrt) 20. SECURITY CLASSIF. (of thl. pes.) "Zr--n~

Unclassified Unclassified . -14----1 ;

MSFC - Form 3292 (May 1969) For sale by National Technj.callnfonnation Service, Springfield. Virginia 2211;1