數位系統實驗Experiment on Digital System

Lab05:

IC design flow and FPGA

Introduction to Verilog HDL

負責助教：葉俊顯 stanley

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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab

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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab

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Digital system

Digital system 數位系統 (digital system) 通常被設計用來實現或完成某一些特殊的功能需求

MP3 player Mobile phone …

一個數位系統可能包含數個不同功能特質的數位電路， 而數位電路一般是使用所謂的半導體技術實作於積體電路

(Integrated circuit, IC) 上

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IC design flow

Product specification

Circuit design

Layout(placement & routing)

Sim/Ver

Sim/Ver

GDS-II

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ASIC and FPGA

當設計者完成 RTL(Register Transfer Level)電路後，若使用製作功能應用導向晶片 (Application Specific Integrated Circuit ， ASIC) 的 EDA tools來進行合成、模擬、驗證，最後，會產生一個 GDS-II檔案。最後，可將此檔案委請晶圓廠製成一顆 ASIC晶片

FPGA/CPLD是一種可依需要做程式規劃的晶片，其中包含許多可被使用的 cells，透過 FPGA廠商提供的 FPGA-EDA tool進行合成、模擬與驗證，最後將所設計的電路燒錄到 FPGA上面

FPGA (Field Programmable Gate Array) – 本課程所使用 CPLD (Complex Programmable Logic Device)

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FPGA design flow

Design ideas

Detailed design

Functional simulation

Implementation(P & R)

Time simulation

Device programming

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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab

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Introduction to HDL

HDL Hardware description language Similar to general-purpose languages like C Modeling and simulation of the functionality of

combinational and sequential circuits Parallel vs. sequential behaviors

Two competitive forces Verilog: C-like language – 本課程所使用 VHDL: ADA-like language

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Introduction to Verilog HDL

C-like syntax/semantics

Basic building block Module

Four kinds of model for circuits Switch Level Model or Transistor Model (npn & pnp …) Gate Level Model (or & and …) Data Flow Model (assign) Behavioral Model (RTL description) (always@() begin … end)

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Design hierarchy

sub_module1

sub_module2 sub_module3

top_moduleinput1

input2

input3

input4

output1

output2

output3

output4

output5

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Identifier

Names of modules, ports, wires and instances are all identifiers

First character must be a letter, and other characters can be letters, numbers or underscore ( _ )

Upper case and lower case letters are different

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Keyword

All keywords are defined in lower case

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Keyword

All keywords are defined in lower case

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Data type

net

reg

parameter

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Data type - net (wire)

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Data type - reg

A reg data type represents a variable in Verilog

Type ”reg” variable stores values, but not necessarily a FF (register)

Are only assigned in an ”always” block task or function

If a reg data type is assigned a value in an always block that has a clock edge expression, a flip-flop is inferred

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Data type - reg

By default, net and register are one-bit wide

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Data type - parameter

Represents constants

Declared by: parameter data_size = 5;

Cannot be changed at run time

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Value Set

Verilog has four value levels

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Operator Priority

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Module

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Module - example

module half_adder (

x,

y,

c,

s

);

// port declaration

input x; // width: 1 bit

input y;

output c, s;

// I/O type and data type

wire c;

wire s;

// functionality or structure

xor (s, x, y); // (out, in, ……)

and (c, x, y);

endmodule

module name

port name

Verilog primitive

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Circuit design using - Four kinds of model

Switch Level Model

Gate Level Model

Data Flow Model

Behavioral Model

Example: Half adder

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module half_adder (

//input

x,

y,

//output

c,

s

);

// port declaration

input x; // width: 1 bit

input y;

output c, s;

// I/O type and data type

wire c;

wire s;

// functionality or structure

xor (s, x, y);

and (c, x, y);

endmodule

x

y

S

C

half_adderx

y

S

C

assign s=x^y;assign c=x&y;

reg s,c;

always @(x or y)

begins=x^y;c=x&y;

end

Data Flow Model

Behavioral Model

Gate Level Model

Example: Full adder (Gate Level Model)

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module full_adder (x, y, z, S, C);input x, y, z;

output S, C;

// internal nets/registers

wire wire01;

wire wire02;

wire wire03;

// functionality or structure

xor xor01(wire01, x, y);

and and01(wire02, x, y);

xor xor02(S, wire01, z);

and and02(wire03, wire01, z);

or (C, wire02, wire03);

endmodule

and01

xor01

x

y

S

Cand02

xor02

z

wire01

wire02

wire03

Example: Full adder (2HA+1OR)

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module full_adder (x, y, z, S, C);input x, y, z; output S, C;

wire wire1, wire2, wire3 ;

// functionality or structure

// module instantiations

half_adder ha1(

//input

.x (x),

.y (y),

//output

.c (wire2),

.s (wire1)

);

half_adder ha2(

//input

.x (wire1),

.y (z),

//output

.c (wire3),

.s (S)

);

or (C, wire2, wire3);

endmodule

x

y

z

HA 1s

cHA 2

s

c

S

C

wire1

wire2

wire3

Instantiation and port mapping

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In order

By name

// in half_adder.vhalf_adder (x, y, c, s);

// in full_adder.vhalf_adder ha1(x, y, wire2, wire1);half_adder ha2(wire1, z, wire3, s);

// in half_adder.vhalf_adder (x, y, c, s);

// in full_adder.vhalf_adder ha1(.x(x), .y(y), .c(wire2), .s(wire1));half_adder ha2(.x(wire1), .y(z), .s(s), .c(wire3));

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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab

Step by Step

Getting Started – Start the Quartus II software

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Create a New Project – Open New Project Wizard (File → New Project Wizard…)

Step by Step

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Specify the working directory and the name of the project

可先新增資料夾請記住 !

Step by Step

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Select design files. Or click “Next” to skip this step Specify device settings - (Here we use the VerLite Device family)

EP1C6Q240C8

Step by Step

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Edit a Schematic File Open a new Verilog HDL file (File → New → Verilog HDL File → OK)

Step by Step

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Write Verilog codeTop module name 一定要跟 Project name 相同 !!

Step by Step

輸入 (input) 輸出 (output)

被加數 (a) 加數 (b) 和 (sum)進位(carry)

0 0 0 00 1 1 01 0 1 01 1 0 1

Half Addera

b

sum

carry

1

:

//File Name ： Half_Adder.v

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:

module Half_Adder(a, b, sum, carry);

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:

input a, b;

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:

output sum, carry;

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:

 

6

:

assign sum = a ^ b;

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:

assign carry = a & b;

8

:

 

9

:

endmodule

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Compiling the Designed Circuit (Processing → Start Compilation)

Step by Step

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Successful compilation

Step by Step

Simulating the Designed Circuit Using the Waveform Editor (File → New → Vector

Waveform File)

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Step by Step

Simulating the Designed Circuit Use node finder to find all the pins(Edit → Insert →

Insert Node or Bus…)

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Step by Step

Simulating the Designed Circuit Selecting nodes to insert into the Waveform

Editor

Step by Step

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沒跑出 pin腳，表示你剛剛忘記 compile

Simulating the Designed Circuit Selecting nodes to insert into the Waveform

Editor

Step by Step

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Simulating the Designed Circuit Select and edit waveform

Step by Step

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Simulating the Designed Circuit Setting of test values

Step by Step

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Performing the Simulation Modify default settings (Assignments → Settings… →

Simulator Settings → Functional → OK)

Step by Step

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Generate functional simulation netlist before simulation (Processing → Generate Functional Simulation Netlist)

Step by Step

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Start simulation (Processing → Start Simulation )

Step by Step

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The result of functional simulation

Step by Step

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輸入 (input) 輸出 (output)被加數

(a)加數 (b)

和(sum)

進位(carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

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Outline

IC Design Flow and FPGA

Introduction to HDL

Write Verilog code using Quartus II

Lab

Lab I

Using Verilog to implement a 1-bit Full Adder

Simulation Result z y x S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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Lab I - Hint

and01

xor01

x

y

S

Cand02

xor02

z

wire01

wire02

wire03

Hint (Gate Level Model)

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Lab II

Using Verilog to implement a 2-bit Full Adder

Simulation Result z1 y1 x1 C1 y2 x2 S1 S2 C2

0 0 0 0 0 0 0 0 0

0 0 1 0 0 1 1 1 0

0 1 0 0 1 0 1 1 0

0 1 1 1 0 0 0 1 0

1 0 0 0 1 1 1 0 1

1 0 1 1 0 1 0 0 1

1 1 0 1 1 0 0 0 1

1 1 1 1 1 1 1 1 1

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Lab II - Hint

and01

xor01

x

y

S

Cand02

xor02

z

wire01

wire02

wire03

and01

xor01

x

y

S

Cand02

xor02

z

wire01

wire02

wire03

x1

y1

z1

S1

C1

x2

y2

S2

C2

wire01

wire02

wire03

wire04

wire05

wire06

or01

or02

xor03

xor04

and03 and04

XC1

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Ref. Instantiation and port mapping

Notice

請勿在桌面建立 Project 及請勿命名中文資料夾

Device family 請確認與 FPGA Chip 符合 (EP1C6Q240C8)

Top module name & Project name 需要一致

確認 module … endmodule 為 keyword 變成藍色字體

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