ΚΕΦΑΛΑΙΟ 3

3

3 -

3.1 3.2 3.3 3.4 3.5 3.6 (Encoders)3.7 3.8 3.9 3.10 /

3 -

3.1

2n m m n

3 -

3.1 : (bits), (. 4)

3 -

3.2 . Combinational Logic DesignM , , , , , ( ), , CAD, HDL,Synthesis (DL): VHDL

3 -

3.2 , : 1/8

3 -

3.2 , : 2/8

3 -

3.2 , : 3/8

3 -

3.2 , : 4/8

3 -

3.2 , : 5/8

3 -

3.2 , : 6/8

3 -

3.2 , : 7/8

3 -

3.2 , : 8/8

3 -

3.2 (simplification) 9input odd: 10 32

: ( blocks, ) - primitive and predefined blocks

(reuse)

3 -

3.2 / CAD CAD: computer aided design/ , , , synthesizers

3 -

3.2 Hardware Description LanguagesHDL (vhdl verilog):

: HDL ( )

3 -

3.2 (Logic Synthesis Flow)icfpga

3 -

3.3 : : : / (, ) (CAD )

3 -

3.3 Boolean

12534F1F2

3 -

3.3 Boolean

T1 = BCT2 = ABT3 = A+T1T4= 2D T5= 2+DF1 = 3 + 4F2 = 512534F1F2

3 -

3.3 T1 = BCT2 = ABT3 = A+CT4= (AB)D T5= AB+DF1 = A+C+ ((AB)D) F2 = AB+D . .

3 -

3.3 ( )123

3 -

3.3 : n 2n 1/6

3 -

3.3 2/6

3 -

3.3 3/6

3 -

3.3 4/6

3 -

3.3 5/6

3 -

3.3 6/6

3 -

3.3 C(X,Y,Z)=.

3 -

3.3 C(X,Y,Z)=m(3,5,6,7) =XY+XZ+YZ

3 -

3.3

3 -

3.4 : boolean ( : ) , k-map, ,

3 -

3.4 1/5 3 . 1 3 ( 0). NAND.

3 -

3.4 : 4bit CD 4bit excess-3 1/5(X)CD=(X+3)excess-3 (5)CD=(8)excess-3, 0101 1000

3 -

3.4 CD 2 Excess-3 2/5X3X2X1 X0F3F2F1F00000000100100011010001010110011110001001101010111100110111101111

3 -


3 -

3.4 CD 2 Excess-3 2/5X3X2X1 X0F3F2F1F0000000110001010000100101001101100100011101011000011010010111101010001011100111001010xxxx1011xxxx1100xxxx1101xxxx1110xxxx1111xxxx

3 -

3.4 K-maps CD2EXCS-3

3 -

3.4 (2 vs 3-level )W= A + BC + BD

X = BC+BD+BCD

Y=CD+CD

Z=D

3 -

3.4 (2 vs 3-level )W= A + BC + BD = A + B (C+D)

X = BC+BD+BCD=B(C+D)+BCD

Y=CD+CD = CD

Z=D

3 -

3.4 CD2EXCS-3 3-level

3 -

3.4 BCD-2-Seven-Segment-Decoder

/:

3 -

3.5 (decoders) (encoders) -Priority Encoder (multiplexers - muxes) (demultiplexers) (adders) (signed numbers)

3 -

3.5 (Decoders) n m

3.5 (Decoders) 1/5 3-8 decoder

3 -

3.5 (Decoders) 2/5 3-8 decoder

3 -

3.5 (Decoders) 3/5

3 -

3.5 (Decoders) 4/5

3 -

3.5 (Decoders) 5/5

3 -

3.5 2-4 Decoder enable (high active)D0D1D2D3A0

A1E

3 -

3.5 2-4 Decoder enable (low active)D0D1D2D3A0

A1E

3 -

3.5 2-4 Decoder enableD0D1D2D3A0

A1E

3 -

3.5 3-8 decoder 2-4 decoders

3 -

3.5 3-8 decoder 2-4 decodersenable

3 -

3.5 3-8 decoder 2-4 decoders

3 -

3.5 Decoder-ORS(X,Y,Z) =m(1,2,4,7) C(X,Y,Z)=m(3,5,6,7)

3 -

3.5 Decoder-ORS(X,Y,Z) =m(1,2,4,7) C(X,Y,Z)=m(3,5,6,7)

F F R, ;

3 -

3.5 Decoder-ORDecoders :

3 -

3.6 (Encoders)

3.6 (Encoders) 1/5 1

3 -

3.6 3.6 (Encoders) 2/5 1

3 -


3 -


A0=A1=A2=

3 -

3.6 (Encoders) 5/5

A0=D1+D3+D5+D7A1=D2+D3+D6+D7A2=D4+D5+D6+D7 0, D0=1

3 -

3.6 (Priority Encoder) 1/4 inputs

X valid bit

3 -

3.6 (Priority Encoder) 2/4 inputs X valid bit

3 -


3 -


Y...

3 -

3.7 (Multiplexers/mux)K 2n , 1 . n

3 -

3.7 2x1 MUX 1/5SB

AFS2x1 MUXSF0A1B

3 -

3.7 2x1 MUX 2/5SB

AFS2x1 MUXABSF0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SF0A1B

3 -

3.7 2x1 MUX 3/5SB

AFS2x1 MUXABSF0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1SF0A1B

3 -

3.7 2x1 MUX 4/5F = AS+ BS

3 -

00

01

B

11

10

0

1

A 1

1

1

1

S

3.7 2x1 MUX 5/5SB

AFS

3 -

3.7 4x1 Mux4x1 MUX

3 -

3.7 4x1 Mux

3 -

3.7 UX: 4 bit 1/3T 2x1 UX(Quad 2x1 MUX)

3 -

3.7 UX: 4 bit 2/3

3 -

3.7 UX: 4 bit 3/3

3 -

3.7 1/4F(X,Y,Z)=m(1,2,6,7)

3 -

3.7 2/4

3 -

3.7 3/4

3 -

3.7 4/4

3 -

3.7 A/1 , 2n n

enable

3 -

3.8 . Combinational Logic DesignM , , , , , ( ), , CAD, HDL,Synthesis (DL): VHDL

3 -

3.8 : alf Adder 2-2 1/9

3 -

3.8 : alf Adder 2-2 2/9S=C=

3 -

3.8 : alf Adder 2-2 3/9S=XY+XY=XYC=XY

3 -

3.8 : alf Adder 2-2 4/9S=XY+XY=XYC=XY

3 -

3.8 : Full Adder 3-2 5/9

3 -

3.8 : Full Adder 3-2 6/9

3 -

3.8 : Full Adder 3-2 7/9

3 -

3.8 : Full Adder 3-2 8/9XYXYZXYZ(XY)XY+Z(XY)

3 -

3.8 : Full Adder 3-2 9/9FULL-ADDER

3 -

3.8 n-bit : RCA(ripple-carry-adder) 1/11

4 bit Addition

3 -


4 bit Addition1011 + 0011

3 -


4 bit Addition1 0 1 1 1011 + 0011

3 -


4 bit Addition1 0 0 0 1 1 1 11011 + 00110

3 -


1 0 0 0 1 1 1 11011 + 001100 1 1 1 0110

3 -


4 bit Addition

3 -


3 -


carry-out adder j carry-in adder j+1 ( 1011+0011) 2? : blocks

3 -

CLA (carry-lookahead-adder)RCA : . Critical Path ( ) C0 Cn n t=O(n) 2n+2 2n+2;

3 -

A3:0+B3:0+c0FAFAFAFA

3 -

A3:0+B3:0+c0

3 -

A0B0c0A1B1

A2B2

A3B3S0S1S2S3c4???

3 -

A0B0c0A1B1

A2B2

A3B3S0S1S2S3c1c2c3c4

3 -

3.8 CLA (carry-lookahead-adder)RCA : .

Critical Path ( ) C0 Cn

n t=O(n) 2n+2

2n+2;CLA, t=O(logn)I: carry 2-level /

3 -

3.8 carry-out; 1/2 j: Sj=AjBjCjCj+1=AjBj+Cj(Aj+Bj)= AjBj+Cj(AjBj)Gj = AjBj generatesPj = AjBj propagates

Cj+1= Gj+ Pj Cj

3 -

3.8 Partial Full Adder (PFA)

3 -

3.8 Full-Adder PFAC2C1

3 -

3.8 RCA PFAs

3 -

3.8 carry-out; 2/2 j: Sj=AjBjCjCj+1=AjBj+Cj(Aj+Bj)= AjBj+Cj(AjBj)Gj = AjBj generatesPj = AjBj propagatesCj+1= Gj+ Pj CjC1= G0+ P0 C0C2=G1+P1C1=G1+P1(G0+P0C0)=G1+P1G0+P1P0C0C3=G2+P2C2=G2+P2(G1+P1G0+P1P0C0)=G2+P2G1+P2P1G0+P2P1P0C0

3 -

3.8 Group Generate PropagateP0-3 = P3 P2 P1 P0

G0-3 = G3+P3G2+P3P2G1+P3P2P1G0

/ 16 64 bit

3 -

3.8 X :RCAvs CLAXOR: (2 gate time delay)

4 bit RCA:

4 bit CLA:

16 bit: 34 vs 10

64 bit: 130 vs 14

3 -

3.9 (unsigned)(. 1)

(signed) (complements)

Y

CD

3 -

3.9 - (, )M 1 (>) - -(-) ; / 2 - msb ( ) (). ;

3 -

3.9 1/2

100000 010101 -

10011 11110-

3 -

3.9 2/20111110 100000 010101 - 001011

111000 10011 11110- 10101

3 -

3.9 : 2

3.10 / 1/4Sub/Add

3 -

3.10 / 2/4Sub/Add

3 -

3.10 / 3/4Sub/Add

3 -

3.10 / 4/4

3 -

3.10 -r 2 r r-1 r=2, 2 1 (2s 1s complement) r=10, 10 9 (10s 9s complement)

3 -

3.10 n 1s: (2n-1)-N bit flipping, ; + (2n-1)-N = 2n-12n-1 - ((2n-1)-N) = 2s: 2n-N 0, 0 =0 bits ls 1, flip msb2n -N = (2n-1)-N+12n - (2n-N) = + (2n-N) = 2n101101001111 1011 010110000

3 -

3.10

- , n + 2n - ( 2s) msb , (>) 2s: 2n-(B-A) 8 83 - 7+5 15

3 -

3.10 - , n + 2n - ( 2s) msb , (>) 2s: 2n-(B-A) =1010100, =1000011

3 -

3.10 A-B 1/15 1010100 2s 10101001s 1010100 1000011 - 0111101 + 0111100 + 10010001 10010000 1+ 0010001

3 -

3.10 A-B 2/15 1010100 2s 10101001s 1010100 1000011 - 0111101 + 0111100 + 10010001 10010000 1+ 0010001

3 -

3.10 A-B 3/15 1010100 2s 10101001s 1010100 1000011 - 0111101 + 0111100 + 10010001 10010000 1+ 0010001

3 -

3.10 A-B 4/15 1010100 2s 10101001s 1010100 1000011 - 0111101 + 0111100 + 10010001 10010000 1+ 0010001

3 -

3.10 A-B 5/15 1010100 2s 10101001s 1010100 1000011 - 0111101 + 0111100 + 10010001 10010000 1+ 0010001

3 -

3.10 A-B 6/15 1010100 2s 10101001s 1010100 1000011 - 0111101 + 0111100 + 10010001 10010000 1+ 0010001

3 -

3.10 A-B 7/15 1010100 2s 10101001s 1010100 1000011 - 0111101 + 0111100 + 10010001 10010000 1+ 0010001

3 -

3.10 A-B 8/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 A-B 9/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 A-B 10/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 A-B 11/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 A-B 12/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 A-B 13/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 A-B 14/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 A-B 15/15 1000011 2s 1000011 1s 1000011 1010100 - 0101100 + 0101011 + 1101111 1101110 -(0010001) -(0010001)

3 -

3.10 - , n + 2n - ( 2s) msb , (>) 2s: 2n-(B-A) =1010100, =1000011A-B 2s and 1s1s: end-around carry 1s: ! bit

3 -

3.10 /

4-bit S=0: A BS=1: A => + 2n- B

3 -

3.10 /

4-bit

3 -

3.10 /

c4=1 s3:s0 c4=0 s3:s0 2s

4-bit

3 -

3.10 (signed integer numbers)MSB (LSB) bit 121 SB0 , 1 H : bits (unsigned signed)

3 -

3.10 (signed-magnitude)msb A n :=(-1)n-1x(an-2an-3..a1a0) 5 01001 = 1 x (1001) = 9, (unsigned 9)11001 = -1 x (1001) = -9, (unsigned 25) 0: +/- 0A:

3 -

3.10 1s: 0 (00..0 11..1) 5 9 = 01001, -9=101102s 0 n bits:. 5 9 = 01001 (unsigned 9, 1s 9)-9= 10111 (unsigned 23, 1s -8)10010 =, 11111 = ...

3 -

3.10 4-bit 1/6

3 -

3.10 4-bit 2/6

3 -

3.10 4-bit 3/6

3 -

3.10 4-bit 4/6

3 -

3.10 4-bit 5/6

3 -

3.10 4-bit 6/6

3 -

6.10 / signed-magnitude+ (+/+ --) magnitudes (+/- -/+) carry msb, ( carry), 2s 2s =00011001, =10100101

3 -

3.10 / signed 2s

2s ( )

6+13, -6+13, 6-13, -6+(-13)

-6 - (-13), 6-(-13)

3 -

3.10 / 2s complement

4-bit

3 -

3.10 Y(overflow) 1000+1001 = 10001 n-bits n+1 bits : , ,

3 -

3.10 (overflow detection)E

carry out msb

+/+ -/- carry-in msb carry-out. ;

Y = (cncn-1)

3 -

3-11 3-12

A CD

3 -

Documents

ΚΕΦΑΛΑΙΟ 3