© 2008 Altera Corporation—Public Designing with Transceiver- Based FPGAs at 40 nm

© 2008 Altera Corporation—Public

Designing with Transceiver-Based FPGAs at 40 nm

2


Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

AgendaAgenda

Serial protocols introduction Signal integrity challenges 40-nm transceivers in FPGAs Protocol implementation examples

PCI Express Gigabit Ethernet

Conclusion

3



Serial Protocols Get FasterSerial Protocols Get Faster

In 2002, serial protocols entered mainstream

Dat

a ra

te (

Gb

ps)

in

lo

g s

cale

1

1985

10

1990 1995 2000 2005 2010

0.1OC3

OC12

1SGX 11’02

2SGX 3’06

4SGX 10’08

Mercury 2’01

AGX 6’07

Protocol standard completion date

OC48

OC192

FC1GigE

XAUI

10GE

CEI-6G

CEI-10G

3G SDI

HD-SDI

SDI

FC2

FC4

CPRI 614M

1.2288G

2.4576G

3.072G

OBSAI 768M

1.536G

PCIe 1.0

PCIe 2.0

PCIe 3.0Interlaken 6G

GPON

FC8

SATA 1.0

SATA 2.0

FC16

SRIO 1.25

SRIO 2.5

SRIO 3.125

4



Signal Integrity ChallengeSignal Integrity Challenge

Electrical signal from point A needs to be delivered to point B Point A: TX - transmitter, we refer to signal @ near-end Point B: RX - receiver, we refer to signal @ far-end: either inside device (RX output) or right before RX pins Via Interconnect: Link (IO card+back-plane+IO card)

A Bnear-end eye

far-end eye

TX RX

RX output

I/O card

backplane

connector

transmit devicereceive device

5



Why the Challenge?Why the Challenge? Inside interconnect:

A B

TX RX

Incident Attenuation + Reflection + Radiation + Coupling Transmitted

6



Degradation is Proportional to Data RateDegradation is Proportional to Data Rate

Collection of customer backplanetransfer functions

3.125 Gbps

6.25 Gbps

8.5 Gbps

10 Gbps

-40 dB is 1%

-5 dB is 56%

-10 dB is 32%

0 dB is 100%

-60 dB is 0.1%

7



Pre-emphasisPre-emphasis What are the benefits?

Makes driving long traces and backplanes above 3.125 Gbps possible Longer traces and/or faster data rates require more pre-emphasis

What does it do? Transmitter compensates for channel degradation

What issues does it solve? Relaxes layout constraints by allowing longer routing traces Allows legacy backplanes, designed for slower speeds, to run faster Improves signal integrity May be used with equalization

Does this differentiate Altera from competition? At par for data rates below 3.125 Gbps Clear advantage above 3.125 Gbps

Proven solution up to 6.375 Gbps with transceiver block in Stratix® II GX FPGA

8



Pre-emphasis Opens Eye on 40” PCB @ 6 GbpsPre-emphasis Opens Eye on 40” PCB @ 6 Gbps

Increasing pre-emphasis levels

Equivalent to driving a backplane @ 6g

3” PCB trace (FR-4 material)

40” PCB trace (FR-4 material)

9



6.25-Gbps Signal Degrades Over 40” of PCB 6.25-Gbps Signal Degrades Over 40” of PCB

Short trace (5”)no pre-emphasis

Long trace (40”)no pre-emphasisNot DC balanced

3 ones, 5 zeroes

Short trace (5”)

Long trace (40”)

1

1

2

2

3

3

4

4

10



6.25-Gbps Signal Improves With Pre-emphasis 6.25-Gbps Signal Improves With Pre-emphasis

3 ones, 5 zeroes

Short trace (5”)

Long trace (40”)

1

1

2

2

3

3

4

4

Short trace (5”)with pre-emphasis

Long trace (40”)with pre-emphasis

DC balanced

11



EqualizationEqualization

What are the benefits? Make driving long traces and backplanes above 3.125 Gbps possible

Longer traces and/or faster data rates require more equalization

What does it do? Receiver compensates for channel degradation

What issues does this it solve? Relaxes layout constraints by allowing longer routing traces Allows legacy backplanes, designed for slower speeds, to run faster Improves signal integrity May be used with pre-emphasis

Does this differentiate Altera from competition? At par for data rates below 3.125 Gbps Clear advantage above 3.125 Gbps

Proven solution up to 6.375 Gbps with transceiver block in Stratix II GX

12



Types of EqualizationTypes of Equalization

Since the interconnect is a linear system we can create an inverse transfer function at the receiver (equalize) to undo the effects of the interconnect

There are two types of equalization Linear and DFE (Decision Feedback Equalizer)

The end goal is to achieve a transfer function with a flat response in the frequency of interest

+ =

Interconnect EqualizerFlat systemresponse

13



Flat System ResponseFlat System Response

+ =Interconnect Equalizer

14



Linear EqualizerLinear Equalizer Part of receiver input stage FFE – Feed Forward Equalization (Linear) Advantage: Requires no prior data knowledge Disadvantage: amplifies crosstalk

TX RXNear-end eye Far-end eye

RX output

Equalizer OFFEqualizer ON

15



Pre-emphasis and Equalization Link Estimator (PELE)Pre-emphasis and Equalization Link Estimator (PELE) What are the benefits?

Simulate links at a fraction of the time compared to HSPICE, save hundreds of hours Automatically derive optimal pre-emphasis and equalization settings

What does it do? PELE is a MATLAB tool that takes transceiver models with s-parameter models of a link to

simulate and automatically derive optimal pre-emphasis or equalization settings What issues does it solve?

With PELE, engineers can move away from trial and error when determining optimal PE settings by using HSPICE alone

There are a number of ways to extract s-parameters of a channel Cadence, Mentor, Agilent or Ansoft have tools that extract s-parameters from layout Agilent has network analyzers to extract s-parameters physical links Both Tek and Agilent have software that convert oscilloscope measurements

into s-parameters

Does this differentiate Altera from competition? Clear advantage for Altera PELE is available when using Mentor SI tools Competition has no PELE equivalent

16



Backplane

TXmodel

RXmodel

Customer provided S-parameters

PELE

Coefficients

PELE: Proprietary EDA Tool Determines Pre-emphasis and Equalization Coefficients PELE: Proprietary EDA Tool Determines Pre-emphasis and Equalization Coefficients

17



Equalization Opens Eye Across 40” at 6.375 GEqualization Opens Eye Across 40” at 6.375 G

Simulated with PELE Eye without equalization

Eye with equalization 17dB equalization

18



Plug & Play Signal Integrity (ADCE)Plug & Play Signal Integrity (ADCE)

What are the benefits? Plug and play End backplane characterization or simulation, ADCE automatically and continuously

adjusts equalizer for optimal signal integrity

What does it do? ADCE is the acronym for Adaptive Dispersion Compensation Engine Receiver automatically and continuously adjusts equalizer settings for optimum

signal integrity

What issues does this it solve? Eliminates tedious task of finding optimal equalization settings through simulation

and lab measurements which typically takes man weeks of time

Does this differentiate Altera from competition? Clear advantage with Plug and Play signal integrity Competition has no ADCE equivalent

19



Altera developed ADCE Automatically monitors

and adjusts the receive equalizer for the best eye opening

PVT continuously monitoredand compensated

Can be run continuously, on power up, or on demand

ADCEADCE


Industry’s 1st 40-nm Transceiver

Building on a solid foundation at 40 nm

21



FPGA Layout (Stratix IV GX FPGA)FPGA Layout (Stratix IV GX FPGA)

Transceiver block,with four 8.5Gbps transceivers, and

two 3.2Gbps transceivers

PCIe hard IP Blocks

High-Speed LVDS IO Bankswith DPA capability

Transceiver, LVDS and GPIOs may be used concurrently – no restrictions

22



Transceiver BlockTransceiver BlockCMU – clock multiplier unit

23



CMU Block in PMA-Only ModeCMU Block in PMA-Only Mode

24



Transceiver ChannelTransceiver Channel

Core logic orPCIe hard IP

Core logic

PMA + PCS

TransmitPIPE

ReceivePIPE

PhaseCompFIFO

PhaseCompFIFO

Byteordering

Byteserializer

Bytedeserializer

8b/10bencoder

8b/10bdecoder

Ratematcher

DeskewFIFO

Wordaligner

Bitdeserializer

Bitserializer

CDR

Pre-emphasis

Equalizer

Bitdeserializer

Bitserializer

CDR

Pre-emphasis

Equalizer

PMA only mode

25


Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation25

Feature Comparison - TransceiversFeature Comparison - Transceivers

Transceiver type PMA + PCS PMA only

Full duplex Yes Yes

Pre-emphasis Yes Yes

Equalization Yes Yes

DFE Yes No

ADCE Yes No

PCI Express PMA requirements Yes No

8b/10b Yes No

Rate matcher Yes No

Phase compensation FIFO Yes No

PMA power 3.125 Gbps 100 mW 100 mW

PMA power 6.375 Gbps 135 mW 135 mW

26


Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation26

Protocol SupportProtocol SupportProtocol HardCopy® IV ASICs Stratix IV FPGAs

3G protocols

PCI Express Gen1 (x1, x2, x4, x8), PCI Express cable

Serial RapidIO® (1x, 4x)

Gigabit Ethernet, XAUI (IEEE 802.3ae), HiGig+

3G basic (proprietary), 3G SerialLite II

CPRI v3.0, OBSAI v2.0/RP3-01 v4.0

SONET OC-3/12/48, GPON

SATA, SAS

SD, HD and 3G SDI, ASI

Serial data converter (JESD204)

SFI 5.1 Up to 8 channels

HyperTransport™ 3.0 Up to 8 channels

6G protocols

PCI Express Gen2 (x1, x2, x4, x8)

HiGig2, CEI-6G (SR/LR), Interlaken, DDR-XAUI, SPAUI

6G basic (proprietary), 6G SerialLite II

6G CPRI/OBSAI

Fibre Channel (FC1/FC2/FC4)

27



What are the benefits? Reduced cost when implementing multi-rate or multi-protocol systems Enable a single hardware to support multiple protocols

What does it do? Dynamically reconfigure transceiver protocol mode at run time without

interrupting adjacent transceivers

What issues does it solve? End customers can provision an optical port for any serial protocol which

previously required a different line card End customers to support different data rates on a backplane, slower data

rates for legacy cards and faster for next-generation systems

Does this differentiate Altera from competition? Clear differentiation due to transceiver block flexibility (2 clock inputs and

inter block lines) Sophisticated dynamic reconfiguration MegaWizard® vs. primitive capability

with Xilinx

Dynamic ReconfigurationDynamic Reconfiguration

28



Dynamically Optimize Signal IntegrityDynamically Optimize Signal Integrity

Change output differential voltage amplitude Optimize transmit pre-emphasis levels Optimize receive equalization levels

29



Dynamic Reconfiguration: Protocol and RateDynamic Reconfiguration: Protocol and Rate

Multi-rate examples Fibre Channel: 1G, 2G, and 4G SONET/SDH: OC3, OC12, and OC48 SDI: SD, HD, and 3G PCI Express: 1.0, 2.0 Proprietary backplane or SerialLite II: 3.125 Gbps and 6.25 Gbps

Multi-protocol examples Multi-service provisioning platforms (MSPP)

SONET, Fibre Channel, and Gigabit Ethernet

30



Dynamic Reconfiguration ExampleDynamic Reconfiguration Example

Each PLL can select from multiple clock sources External clock Internal PLD clock Clock from adjacent

transceiver block

Each transceiver channel can select either PLL PLL0 or PLL1

Example: SONET and GigE Each transceiver can be

dynamically configured for OC3, OC12, OC48 or GigE

31



Dynamic Reconfiguration BlockDynamic Reconfiguration Block

One dynamic reconfiguration block is shared by up to 4 transceiver blocks

MIFs (memory initialization file) store unique transceiver settings

Vod, pre-emphasis andequalization settings

data rate protocol settings input clock

MIFs can be stored in on-chipor external memory locations

Transceiver channels are modified via the dynamic reconfiguration block


PCI Express Implementation

33



Hard IP for PCI Express (Stratix IV GX FPGA)Hard IP for PCI Express (Stratix IV GX FPGA)

(*) LMI- Local Management Interface(**) DPRIO- Dynamic Partial Reconfigurable Input/Output

1. Non PCI Express cores (XAUI, GbE, SRIO, etc…)2. Soft PCI Express IP protocol stack3. Soft PCI Express IP transaction layer over hard IP DL and PHY MAC 4. Hard Gen1/Gen2 x8, x4, x1 EP/RP hard IP (HIP) protocol stack

Transaction layer (= TL)

Transaction layer over HIP

Datalink layer

PHYMAC

PMAPCSPMAPCS

PMAPCSPMAPCS

PMAPCSPMAPCS

PMAPCSPMAPCS

PIP

E-2.0

Quad 1

Quad 2

HIP bypass

TL bypass

PLD fabric logic

Userapplication

Hard IP PCIe block

Parallel access

LMI (*)

DPRIO (**)

Transaction layer

Data link layer

Phy MAClayer

Non PCIe applications

Soft IP PCIe protocol stack

4

3

2

1 Stratix 4 GX transceivers

TL

Address ECC

PCS/PMAPCS/PMA

PCIe hard IPPCIe hard IP

Soft logicSoft logic

34



Hard IP Feature Set Hard IP Feature Set

High-performance applications PCIe 1.1 / 2.0 compliant protocol stack Integrated TL, DLL, PHY, MAC layers 2 - 4 hard IP cores per device

Feature rich x1, x4, x8 initial link width configurations x2 mode supported through down configuration 125- or 250-MHz application layer clock rate supported Configurable maximum payload size (128, 256, 512, 1024, 2048

bytes) 1 or 2 virtual channels 64-bit Avalon®-ST in all modes 128-bit Avalon-ST in Gen1 x8, Gen2 x4, and Gen2 x8

35



Soft IP CoreSoft IP Core

High-performance, feature-rich IP core

SERDES x1

SERDES x1

SERDES x1

SERDES x1

PCI Express IP core

x1 x4 x8

PIP

E in

terfa

ce

PC

SP

CS

PC

SP

CS

Physical layer

Physical coding sub-layer

Upper protocol layers

Proven solution ~150 licenses issued PCI Express 1.1 compliance Extensive performance benchmarking data across multiple chipsets/platforms Additional interoperability with multiple ASSPs

Flexible and feature rich Easy timing closure with support for incremental compilation Easy integration using SOPC Builder (x1, x4) Configurable maximum payload up to 2 Kbyte and configurable retry buffer Optional end-to-end cyclic redundancy code (ECRC) generation/checking and advanced error reporting (AER) Flexible reference clock support (100, 125, or 156.25 MHz)


10-Gigabit Ethernet Reference Design Features

37



10-Gigabit Ethernet Reference DesignXAUI and XGMII Interfaces10-Gigabit Ethernet Reference DesignXAUI and XGMII Interfaces

PMD,copper, or

optical

10-GbE MAC

Mgmt.

Mgmt.

Hard PCS10GBase-X

(8b/10b)

Hard PMA10GBase-X(4 x 3.125-Gbyte Tx)

Networkinterface

Systeminterface

Altera® FPGA (– GX)Standard PHY

product

Mgmt. slaveinterface

Hard silicon

Soft core

10-GbE reference design

XAUIAvalon-ST

Avalon-MMMDIO - MDC

10-GbytePHY

device

10-GbE MAC

Mgmt.

Mgmt.

Networkinterface

Systeminterface

Altera FPGA Standard PHYproduct

Mgmt. slaveinterface


XGMIIAvalon-ST

Avalon-MMMDIO - MDC

32-bit@ 312.5 MHz

38



10-Gigabit Ethernet Reference Design10-Gigabit Ethernet Reference Design

Configuration options 10-Gbps Ethernet MAC + hard PCS + XAUI PMA 10-GbE MAC with XGMII parallel interface

Supported devices Stratix II, Stratix II GX, Stratix III, Stratix IV (prelim),

and Arria® GX FPGAs

39



10-Gigabit Ethernet MAC Detailed FeaturesEncapsulation10-Gigabit Ethernet MAC Detailed FeaturesEncapsulation

Full duplex operation supporting 10-Gbps Ethernet data rate IEEE 802.3ae 2002 10-Gbps Ethernet standards compliant Easy MegaWizard II user configuration software Transmitter (TX) data encapsulation and receiver (RX) de-capsulation

Tx frame delimiting and Rx frame synchronization per Ethernet frame definition (IEEE 802.3 clauses 3, 4, and Annex 4A) Preamble and start of frame delimiter (SFD) generation and detection

MAC address and VLAN tag transparency Promiscuous (transparent) mode: No Tx source MAC address and FCS insertion and no Rx

destination MAC and VLAN tag recognition/filtering and FCS removal Rx error frames still filtered

Non-promiscuous mode: Tx source MAC address and FCS insertion and Rx destination MAC and VLAN tag filtering and FCS removal; broadcast address filtering in Rx Option: Rx address recognition and filtering two destination MAC addresses,

register configurable, and broadcast MAC address

Transparently passing Tx frame length/type field and checking Rx frame

Pad insertion and removal for shorter-than minimum-length frames

40



10-GbE MAC Detailed FeaturesEncapsulation and Interfaces10-GbE MAC Detailed FeaturesEncapsulation and Interfaces

Tx data encapsulation and Rx data de-capsulation (cont.) Tx 32-bit CRC (FCS) generation and insertion Tx incomplete frame terminate and recover Rx error detection: CRC, preamble, length format, and runt Rx error frame drop or pass-through; register configurable Configurable Tx inter-frame gap insertion range

Minimum 64-bit times to dynamically adjust for Tx data rate adaptation to OC-192 or other data rates

Deficit idle counter support Frame length range: 64 bytes to 16 KBytes super-jumbo

Interfaces External

XAUI XGMII Option: PHY device management MDIO-MDC (compliant with IEEE 802.3 clauses 45 and

22) Internal MAC datapath interface with PCS or serial transceiver: XGMII Internal system datapath: Avalon-Streaming bus, 64 bits @ 156.25 MHz, big endian

Option: Tx and Rx FIFO, selectable size, configurable AF and AE flags Internal management (IP configuration and monitoring): Avalon-MM bus, 32-bit Internal PCS and serial transceiver management path: native internal management bus

41



10-GbE MAC Detailed Features Flow Control, Management, and Performance10-GbE MAC Detailed Features Flow Control, Management, and Performance Flow control

Compliant with IEEE 802.3 annex 31B and clause 30 Register-configurable loss-less flow control Auto Tx control pause packet generation and transmission based on Rx FIFO flags Rx XON/XOFF control pause packet recognition and stop Tx

Layer, network management, and OAM Compliant with annex 4a and clause 30 Tx and Rx enable/disable Separate reset controls: MAC, FIFO, Avalon-MM Support all the relevant full-duplex 10-GbE DTE basic, mandatory, and recommended management

capabilities and statistics Option: Statistics counters supporting RMON (RFC2819), Ethernet type MIB (RFC 3635), and interface

group MIB (RFC 2863) Option: Local and line loop-back (inside RS) Single error injection in Tx

Flexible clock domains Single core clock domain, or: Core + FIFO system side + Avalon-MM management bus

Performance Full-duplex throughput rate of up to 10 Gbps in each direction

Resource requirements 5050 LEs, 12 x M512, MAC + mgm’t registers + statistics + MDIO-MDC (no FIFO)

42



Datapath

Mgmt. path

Standardmodule

Optionalmodule

Tx FIFOCTLand

buffer

Statisticsmodule

10Gb Ethernet MAC

Internalsystem

datapathinterface,Avalon-ST

MemoryInternal

management bus,

Avalon-MM

Data

Ctrl and

Clk

MACTx CTL MAC

XGMIITx CTL

MACXGMII

Rx CTL

Rx FIFOCTLand

buffer

Data

Ctrl and

Clk

MACRx CTL

Control andclock

Mgmt. buscontrol

and registersmodule

MAC only: XGMIIMAC+PCS: pseudo-XGMII

10GBase-XPCS +

XAUI PMA

Quadserial

transceiverin

GX devices

XAUIinterface

ExternalPHY device

mgmt. module

MDIO/MDC

To/fromstandard 10-GbE

PHY device


Native mgmt. bus

Non-promisc.Tx logic

Rx packetfilter

10-GbE Reference Design Block Diagram10-GbE Reference Design Block Diagram

43



Datapath

Control path

Switchfabric

Ethernetswitch

Switch fabric card

FPGA

Std.product

Framer/Ethernet

MAC/Mapper

Classifier,traffic mgr.,

SPI-4packet bridge

NPU

Co-processorMemory

Memory

Switchfabric

interface

. .

Control logicand

Ethernet MAC

EthernetPHY

Network line card

Externalnetworkinterface

• •

• •

x N x 2

x 2Manager cardcontrol CPU

Control logicand

Ethernet MACEthernet PHY

System managercard

x 2

Memory

Ethernet PHYManagement

interface

Line cardcontrol CPU

Memory

Ethernet PHYManagement

interface

100M/1Gb MAC

Nx10GbE MAC Nx10GbE MAC

A 10-GbE Application ExampleWireline: Switch/RouterA 10-GbE Application ExampleWireline: Switch/Router

44



ConclusionConclusion

Stratix IV GX devices are industry’s first 40-nm transceiver-based FPGAs

Altera offers best signal integrity features with data rate support up to 10 Gbps

Protocol implementation is greatly simplified due to transceiver block features and hard IP

Documents

© 2008 Altera Corporation—Public Designing with Transceiver- Based FPGAs at 40 nm