© 2003 Xilinx, Inc. All Rights Reserved Digital Filtering

© 2003 Xilinx, Inc. All Rights Reserved

Digital Filtering

Digital Filtering - 3 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Objectives

After completing this module, you will be able to:• State various filters supported in System Generator• Describe the FIR filter implementation and understand how to take

advantage of certain filter parameters• Describe the integration of FDATool block in System Generator


Outline

• Introduction• FIR Filters

– DA Filters– MAC FIR Filters

• CIC Filters• IIR Filters• Generating Coefficients

– FDATool and XFLDATool– Exporting Coefficients

• Simulink Tips and Tricks– Plotting Functions– Spectrum Scope– White Noise


Introduction

• Digital filters are the most common of functions found in DSP systems• Following blocks are supported by System Generator for digital filtering

– FIR block– CIC block

• Digital filtering technique to be used will depend on several factors– Sample rate– Sample width– Coefficients profile– Clock rate


Outline







DA FIR Filter Block

• Implements a single channel, single and multi-rate finite-impulse response (FIR) digital filter

• In multi-channel, a single FIR filter is used in time division multiplexing mode so that the amount of resource utilization virtually remains same at the expense of reduced sample rate

• The DA FIR filter provides optional ports for coefficient reloading– When a reload sequence is initiated, the filter stops

accepting new data input samples and begins accepting new filter coefficients

– The amount of time required for the filter to reload is a function of the filter length and type

Reloading Option

Fixed Option


DA FIR Filter

• Supported features– Parameterizable coefficient width– Two to 1024 taps– One to eight channels– Polyphase interpolation/decimation– Optimization for symmetry, half-band,

interpolated filters– Parallel, serial and multi-clock per

output implementation


Twos ComplementSerial Multiply

• One bit at a time:


SDA 1-Tap FIR Filter

X0

PartialProductROM

A01

N BITS WIDESAMPLE DATA

+/- Z-1

Scaling Accumulator

LUT contains two locations

00000...0C0

A00

1

Parallelto serial converter


= Sign Extension

-23 22 21 20

C0 = 1 0 0 1 (-7)X0 = 0 1 1 1 ( 7)X

( 1 0 0 1 ( 1 0 0 1 ( 1 0 0 1 (0 0 0 01 1 0 0 1 1 1 1 (-49)

-23 22 21 20

C1 = 0 1 1 0 ( 6)X1 = 0 1 0 1 ( 5)X

0 1 1 0) 0 0 0 0 ) 0 1 1 0 ) 0 0 0 0 )0 0 0 1 1 1 1 0 ( 30)

1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 = 1 1 1 0 1 1 0 1

++++

(-1)(-14)(-4)(0)(-19)

(Serial-Data / Tap-Parallel Multiply)

Distributed Arithmeticfor a 2-Tap Filter

• Partial products of equal weight are added together before being summed to next higher partial product weight

• Create look-up table of summed partial products



LUT contains all possible sums of the partial products

00

01

10

11

0000...0C0

C0 + C1

C1

X0

X1

A0

A1

1


Partial

Product

ROM+/- Z-1

Scaling Accumulator


0000...0C3

+


X0

0000...0C0

X1

A0

A1


0000...0C1

+

+/- Z-1

Scaling Accumulator

1

X2

0000...0C2

X3

A2

A3

1

+Partial

Product

ROM

1


SDA 8-Tap FIR FilterN BITS WIDE

SAMPLE DATA

+ +/- Z-1

Scaling Accumulator

PartialProductROM

X0

X1

A0

A11

X2

X3

A2

A3

1

1

PartialProductROM

X4

X5

A0

A11

X6

X7

A2

A3

1

1 4 -input LUT contains all possible sums of the partial products

Pre-Adder

1


fclk = 200 MHz for both processor and FPGA

B = data sample precision for FPGA

Xilinx DA FIR Performance

0 50 100 150 200 2500

1000

2000

3000

4000

5000

6000

Filter Length (Taps)

Per

form

ance

(M

MA

Cs/

s)

Serial FPGA FIR

Dual MACDA FIR B=8DA FIR B=12DA FIR B=16

10

20

30

40

50

60

Sam

ple

Rat

e (M

SP

S)

Single MAC DA FIR B=8 DA FIR B=12DA FIR B=16

0 50 100 150 200 2500

Serial FPGA FIR

Filter Length (Taps)


Exploiting Filter Symmetry

• Impulse response often possesses symmetry– Symmetry or negative symmetry

• Symmetry is exploited to produce efficient FPGA implementation– Uses half the number of multipliers, thus a large size reduction– Number of clock cycles increases by 1 due to pre-adder

a3 a5(=a3)

a2

a1

a0 a4 a6(=a2)

a7(=a1)

a8(=a0)

Symmetric FIR - Odd number of coefficients Symmetric FIR Implementation

++

a0

x(n)

y(n)

Z-1 Z-1

Z-1 Z-1

Z-1

Z-1

Z-1

Z-1

+ +

a1 a2 a3 a4

++ + +


Half-Band FIR

• Odd number of coefficients (every other coefficient is zero)

• Half-band implementation (for odd number of coefficients)

0 2 4 6 8 10-0.2

0

0.2

0.4

0.6

COEFFICIENT INDEX

NUM. TAPS = 11

x (n )

y (n )

Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1Z-1 Z-1

+++ +++

a10a8a6a5a4a2a0


Multi-channel

C0

X0

C1

C2

• • •

Up to 8 channels

N-bit Sample Data

K TAPS LONG

K SUMs

SUM

FIR FILTER

Out

Ch 1Ch n Ch 2 . . .

Output sample rate =FIR Sample rate

# of channels

Sample rate reduced as more channels are processed

Chan n - X0 ……. Chan 2 - X0 Chan 1 - X0



Ch 1Ch n Ch 2 . . .


Interpolation TheoryPr

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Interpolation is used to increase the number of samples representing a waveform…….

An original waveform represented by few samples has a frequency spectrum below its Nyquist rate

Sample rate increased by injecting ‘zero value’ samples between originals (3 in this case).

Original spectrum is aliased by the injected zeros

A low pass filter removes the aliased responses to produce a waveform the same as the original but containing more (4×) samples.


Multiply by Zero - No Thank You!Pr

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In the interpolation process we also have a filter, but this time we have data samples which are zero and therefore would also like to avoid multiplications where these are the input…….

a b c d e f e d c b a

‘0’

S(n)0 0 0 0 0 0 0 0

We can see that during any interpolated sample period, only some of the taps (1 in 4 for interpolate by 4) contribute to the output sample. Hence many of the multipliers and the majority of the summation process is inactive. We will also have a lower saturation level which may reduce the number of bits required.


‘0’

S(n)0 0 0 0 0 0 00

In the next interpolated sample period a different set of coefficients become ‘active’. This means that all coefficients are required over the interpolation cycles, but not all at the same time.

Many registers used to store zero

Interpolate by 4


Polyphase Filter StructurePr

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The zero data sample injection process can be re-organised into the polyphase structure. This is a set of filters operating at the input sample rate with each containing the coefficients required to form one new interpolated sample…...

a e c

S(n)

b f b

c e a

d d

Multiplexer scans results in sequence required.

Registers are only required to store real data samples and are enabled at the original sample rate. Phase filter results

captured at the original sample rate.

Only the multiplexer has to perform at the interpolated rate. Phase filters are smaller and have more time.


Decimation TheoryPr

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Decimation is the opposite to interpolation as it takes a high sample rate and reduces it to a lower sample rate. However, it is very similar to interpolation in many ways…...

An original waveform Requires a high sample rate because the signal contains high frequency components. However, only the lower portion of the spectrum is required.

A low pass filter removes the high frequency components contained in the original signal that would be aliased below the new Nyquist frequency if samples were simply to be decimated.

The filtered signal contains only low frequencies. This can then be represented by a lower sample rate achieved by decimation In this example only 1 in every 4 samples are retained (decimation by 4). The other samples are simply thrown away!


All That Hard Work Going To The Dustbin!Pr

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It appears that after all the work of filtering at a high sample rate, we simply throw away most (or at least half) of all the hard work that has been done…...

LPF100MHz100MHz

25MHz

Capture 1 in 4 samples100MHz filter

Clearly it would be much better to only calculate the samples which are retained and ignore the others….


12341234

This diagram shows the input samples passing through a normal FIR filter.

4

123

Only calculations where samples are in these taps

will be retained.

Samples are only used after they have moved 4-taps, but then all

samples and coefficients are used.

Notice how the red sample is only used in the taps with

coefficients ‘c’, ‘e’, and ‘a’.


Decimation Filter StructurePr

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It should not be a big surprise to realise that this is also a polyphase structure…..

a e c

b f b

c e a

d d

+

+

+

4

3

1

2

Registers at the input to each filter capture 1 in every 4 samples. It is critical that the order is correct. The first

sample received is the one that must appear to pass further along the shift register before it is used.

Adder tree combines all phase results to form single output sample.

Filters have 4 input sample periods to complete processing of their share of the input samples

and coefficients. Results are then passed to the final phase summation process.


Interpolated FIR Applications

• Interpolated filter and image rejection filters

• Interpolated FIR implementation for narrow-band filters

Interpolated

Filter

M(zk)

Image Rejection

Filter

I(z)

x(n) y(n)

Type ‘InterpolatedFIR’ to view the example

x(n) Z-k Z-k Z-1 Z-kZ-k

++++

anm-1a3a2a1a0

y(n)


The sample is serialized and processed 1 bit per clock cycle. 8 clock cycles are thus required to process the whole sample

The sample is serialized and processed 2 bitsper clock cycle. 4 clock cycles are thus required to process the whole sample

The sample is serialized and processed 4 bits per clock cycle

The sample is processed in parallel 8 bits per clock cycle

b0 b0

b0

b3

b4

b7

b3

b4

b7

b0

b0

b7

Serial-DA Parallel-DA

Multi bits per clock cycle

Trade Clock Cyclesfor Logic Area

20Ms/s 160Ms/s

Hardware Over-sampling = 8

b0

b7

HardwareOver-sampling = 1

Trade Clock Cycles for Logic Area




Filter Throughput

• The filter sample rate is a function of:– Clock frequency, fclk– Input data sample width, B– Hardware over-sampling rate– Coefficient symmetry and number of channels

• One channel, FIR filter– Over-sampling = fclk / fs

• Fully serial implementation– Non symmetric: Hardware over-sampling rate = B– Symmetric: Hardware over-sampling rate = B + 1


Questions

• How many clock cycles per input are required for a fully parallel 12-bit data, 20-tap symmetric filter?

• The requirement for a filter is to run at 25 MSPS. A 100-MHz system clock is available on the board. What should the hardware over-sampling rate parameter be set to for 8-bit data?

• How many clock cycles per input are necessary to process in serial an 11-bit data, 31-tap symmetric filter?


MAC Filter

• The output of the filter at time n

– Can be implemented using single multiply and accumulate (MAC) engine– Can also be implemented using n MACs (parallel technique), or– Using between 1 and n MACs (MAC Farm technique)

• Samples can be stored in– Distributed RAM– Block RAM– SRL16E

• Embedded multipliers may be considered for this architecture

• No high-level block in the System Generator• There is a customizable core available• A reference design is available in Reference Blockset

yn = xn-i hii=0

N-1

Samples 92 × 8

Coefficients 92 × 12

Samplein

Sample Address

Coefficient Address

D Q CE

+

+ D Q

Capture of final result • Simple register • Supports result size

8

12

20 26 26

Full Multiplier • Sample-width × max Coeff-width

Sample Memory Cyclic RAM buffer Depth = Taps Width = Sample size

Accumulator • Sample-width depends on number of taps


MAC FIR Core

• The Xilinx MAC FIR core implements a highly configurable, high-performance, and area efficient FIR filter– Single-rate polyphase decimators and interpolators are supported– Multiple data channel operation is supported for all filter types– Symmetry in the coefficient set is exploited for single MAC implementations to

increase overall performance and minimize resource utilization– Data-paths provide full-precision arithmetic to avoid overflow


Transpose FIR Structure

k0 k1 k2 k3

s(n)

y(n)

Normal FIR

k0

s(n)

y(n)

Transpose FIR

k3 k1k2

‘0’

Note : Coefficient order reversed

• The Normal FIR Filter structure can be implemented using the MAC Core in a parallel technique. In this case samples stored in registers.

• Maybe implementation issues as number of taps increase due to adder tree

• The Transpose FIR Filter structure uses adder chain

– No high level block in System Generator implemented using basic elements


Filter Selection

10 MHz100 kHz 1 MHz

Sample Rate

250 500 750 2.5 5.0 7.5 25 50 75

100 MHz250 MHz

10 kHz

25 50 7575

Distributed RAMBlock RAM

External RAM

MAC Engine Sample Rate = Number of TapsClock Rate

or =½ × Number of Taps

Clock Rate(Symmetry)

1 MAC Engine

SDA Sample Rate = Sample-bits (+1)

Clock Rate

Serial Processing Techniques

Full Parallel FIR Sample Rate = Clock Rate

Parallel Techniques

SDA semi-parallelMulti-bit Processing

Sample Rate =Sample-bits (+1)

Clock RateX BAAT


Outline







CIC Filter Block

• Cascaded integrator-comb (CIC) filters are multi-rate filters used for realizing large sample rate changes in digital systems

• Both decimation and interpolation structures are supported

• CIC filters contain no multipliers; they consist only of adders, subtractors and registers

• They are typically employed in applications that have a large excess sample rate; that is, the system sample rate is much larger than the bandwidth occupied by the signal

• Frequently used in digital down-converters and digital up-converters


CIC Decimator

• The CIC decimator consists of a cascade of integrators followed by a resampling switch and a cascade of differentiators

– The integrator section consists of N ideal integrator stages operating at the high sampling rate fs

– The comb section operates at a slower rate fs/R, R is the integer rate change factor• The differential delay M in the differentiator chain may be defined by the user to

be either 1 or 2• To ensure high system clock frequencies, the CIC decimator is actually

implemented using the pipelined architecture


CIC Interpolator

• CIC Interpolator consists of a cascade of differentiators followed by a cascade of integrators

– Data is presented to the filter at the rate fs/R where it is processed by the differentiators

– The rate expander causes a rate increase by a factor R by inserting R-1 zero valued samples between consecutive samples of the comb section output

– The up-sampled and filtered data stream is presented to the output at the sample rate fs


CIC Block Parameters

• Filter Type : Interpolator or Decimator

• Sample Rate Change : 8 to 16384 (inclusive)

• Number of Stages : 1 to 8 (inclusive)

• Differential Delay : 1 or 2


Outline







IIR Filters

• Lower order than FIR filter, i.e., less number of taps• Characterized by having infinite impulse response• Involves using previously computed values of the output signal as well as the

input signal in the computation of the present output• Build using basic blocks (multipliers, registers, adders)

b1

b2

b3

b4

a2

a3

a4

a5

Sin Sout

a1

All input related calculations have bit-widths defined by the input samples

Basic algorithm assumes no additional sample delays in feedback path

Feedback path must support the largest value expected and can result in large bit-widths

A second order filter consists only of coefficients a1, a2, a3, b1, and b2


IIR Filter Example

• A 2nd order IIR filter can be built using five multipliers, five registers, and an adder tree

– using constant multipliers implemented in LUTs

– Using embedded multipliers • Multipliers and adder tree are of full

resolution, however need a quantization block at the output of the adder tree to control the output width

Type ‘sysgenIIR_DFormI’

to view the example


Outline







Xilinx FDATool Block

• The Xilinx FDATool (Filter Design and Analysis Tool) block provides an interface to the FDATool software available as part of the MATLAB Signal Processing Toolbox

• Xilinx FDATool provides a powerful means for defining digital filters with a graphical user interface

• The block will not function properly and should not be used if the Signal Processing Toolbox is not installed

• This block provides a means of defining an FDATool object and storing it as part of a System Generator model

• Does not use any hardware resources


FDATool Block Usage

• Copy an FDATool block into a subsystem where a filter is defined• Double-clicking the icon in your Simulink model opens up an FDATool session

and graphical user interface• The filter is stored in internal data structure of the FDATool block• The coefficients can be extracted using MATLAB helper functions

– xlfda_numerator(‘FDATool’) returns the numerator– xlfda_denominator(‘FDATool’) to returns the denominator


FDATool Session


Effect of Quantizing


Exporting Coefficients

• Once the filter is designed, coefficients can be exported using File Export from the FDATool Block GUI

• Can be exported to―Workspace (provide variable name)―Text-File (provide text file name)―M-File (provide M-file name)


Saving Coefficients

• If the FIR filter block (or any other Xilinx block) is using variables from the workspace, it is desirable to load those variables (e.g., filter coefficients) from a file and have them loaded every time the file is opened

• To do this, create a MATLAB .m file that contains the coefficients in a vector. An example below shows the file Load_coef.m:Coef = [-0.0043 0.0024];

• Use set_param to set the Simulink model parameter "PreLoadFcn" set_param(‘design_name’,’PreLoadFcn’,‘Load_coef’)

• The PreLoadFcn will run a script to create the variable and place it in the workspace

• The MATLAB path must be set to the location of the .m file for MATLAB to find the function


Saving Coefficients

• Alternatively, create an M-file with coefficients defined in it

• Right-click anywhere on the design sheet and select Model Properties to open a form

• Enter the filename (without .m extension) in the “model pre-load function” field of the “Callbacks” tab and click OK


The ProductYou are DSP Designer at Cyberdyne Systems. Your company is investigating using Digital Filters instead of analog for their Security Tag detectors in an attempt to improve performance and reduce cost of the overall system. This will enable them to further penetrate the growing security market space. The specification of the single channel, single rate filter is specified below:

Cyberdyne has chosen to go with FPGAs due to their flexibility, time to market and performance advantages over DSP Processors. Your HDL design experience is limited and hence System Generator for DSP appears to be an excellent solution for implementing the filter in an FPGA, as you are already familiar with The MathWorks products.

Band Pass Filter

Sampling Frequency (Fs) = 1.5 MHzFstop 1 = 270 kHzFpass 1 = 300 kHzFpass 2 = 450 kHzFstop 2 = 480 kHz

Attenuation on both sides of the passband = 54dBPass band ripple = 1


Stage 1: The Prototype

Your manager Miles Booth has requested that you create a prototype of the filter to be implemented on their Virtex-II Pro™ prototype board that is almost complete. The prototype must be finished as quickly as possible for the imminent Aggressive Security convention, which is the industry’s largest convention of the year so it must not be missed.

Band Pass Filter

Sampling Frequency (Fs) = 1.5 kHzFstop 1 = 270 kHzFpass 1 = 300 kHzFpass 2 = 450 kHzFstop 2 = 480 kHz

Attenuation on both sides of the passband = 54dBPass band ripple = 1

Data Bit Width = 8 BitsCoefficient Bit Width = 12 Bits


Lab 4: Design a FIR Filter

• In this lab, you are asked to design a bandpass FIR filter • Use the FDATool to create the coefficients and pass to the FIR block• Use the DA FIR filter token to simulate and implement this filter


Outline







Basic MATLABPlotting Functions

• Commonly used general and plotting functions for system generator designs:

– plot(y, x) - general plotting function– stem(x) - useful for viewing an impulse response

– Hold on - allows more than one plot on the same figure– Hold off - switches off hold on– Grid - displays a grid on the plot

– fft(x, 1024) - performs a 1024pt FFT on data ‘x’;– abs(x) - use this to find the magnitude of number– Angle (x) - use this to find the phase of a number

• Use help for further information on usage

Stem plot of a Low Pass Filter’s impulse response

Plot of the Magnitude Frequency response of the same Low Pass Filter


Using the Spectrum Scope

• The Spectrum is extremely useful for performing a frequency analysis on your design and can be found in the DSP blockset DSP sinks library

• As no System Generator designs will use frame-based data, the input must be “buffered” (under the Scope properties). The size of the buffer determines the resolution of the FFT performed

• Use overlapping to avoid the discontinuities of using finite data

• Use the “Axis properties” to control the axes scale and units


Type ‘SpectrumScope’ to view the example

Using the Spectrum Scope

• The example takes two chirp signals (frequency-varying Sine Waves), adds them together and views the results on the Spectrum Scope

• Note: Be aware of the window that is being used by the scope, especially when analyzing small data sets. The default is hamming and can only be changed by looking under the mask and changing the property on the window block


Type ‘WhiteNoise’ to view the example

Using White Noise

• An excellent block to complement the Spectrum Scope is the Gaussian White Noise block (Communications Blockset Comms sources). This block outputs a signal over all frequencies below the Nyquist frequency

• Useful to view filter cutoffs• Make sure you do not output vectors or

frame-based data as System Generator designs do not accept them

Documents

© 2003 Xilinx, Inc. All Rights Reserved Digital Filtering