© 2002 ® Wireless Solution Update Asif Batada Marketing Manager, Wireless Business Unit Asif Batada Marketing Manager, Wireless Business Unit

© 2002

®

Wireless Solution UpdateWireless Solution Update

Asif Batada

Marketing Manager,

Wireless Business Unit

Asif Batada

Marketing Manager,

Wireless Business Unit

© 2002®

AgendaAgenda Mobile Base-station Architecture

Basics of Digital IF and Digital Predistortion Linearizer

RF Card Architecture

Predistortion Linearizer Implementation

Conclusion

© 2002®

Antenna

RNC I/F

IP Interface

Switch Controller

A/DD/A

Base Band SignalProcessing

Switch I/FHost Processor

(CPU)

Clock Generator

PLD Application

Control Board

Channel Card

RNC

Digital IF

DigitalPredistortion Linearizer

Mux/De-Mux

HostuP

RF Card

Base-Station ArchitectureBase-Station Architecture

LVDSw/CDR

ATMproc

PA

LNA

© 2002®





Conclusion

© 2002®

Digital IF OpportunityDigital IF Opportunity Digital IF is a high volume application for FPGA:

Macro BTS can be configured into two different ways: 2 carriers for 3 sectors 1 carrier for 6 sectors

Each BTS hasDigital IF Implementation: 6 x EP1S20Predistortion Implementation: 6 x EP1S10

6 x EP1S20 + 6 x EP1S10 per BTS

1 carrier(5Mhz for UMTS)

6 Sector Cell

60

3 SectorCell

120

© 2002®

Traditional IF-Based TransmitterTraditional IF-Based Transmitter

Issues with traditional transmitter Not flexible to support multiple standards Non-ideal local frequencies are source of noise RF and analog components of radio are more difficult to

manufacture and have higher reliability issues Higher cost

BBfilter

BBfilter

+90ºf1

IFfilter

RFfilter

f2

Amp PA

I

Q

DAC

DAC

© 2002®

Digital IF Digital IF S

ym. M

appe

r

FIRfilter

NCO

FIRfilter

f2

Amp PA

IFfilter

RFfilter

Digital Up-Converter

With the advancement of data converter technology (100Msps +), it is possible to sample at IF (intermediate frequency) and do Channelization in Digital domain

Advantages of Digital IF Channel selection can be done in digital domain Higher precision in frequency selection and shorter settling time of DDS Good amplitude and phase balance Extremely linear phase and very low shape factor of base-band filter

DAC

© 2002®

Predistortion LinearizerPredistortion Linearizer RF stage (transmitter) uses a linear Power Amplifier (PA)

to boost the signals Linear PAs are very expensive

Some cases it makes up half the cost of BTS Non-Linear PAs are cheaper

LDMOS based technology LDMOS introduces distortion of its own

Predistortion in digital domain Pre-distort the signal so that when it goes thru PA, the overall

response is linear Common technique – Look-up Table based approach

Store the points on the transfer function in a look-up table One of our customers evaluating 20K400E for this application Nios is well suited

Input Power

OutputPower

Add Predistortion

© 2002®





Conclusion

© 2002®

RF Card – 1st Generation DesignRF Card – 1st Generation Design Customers have either designed their own Digital IF chip (w/o DPD)

or are using ASSP (mostly GrayChip)

Limitations with current implementation: Custom Filter Specs – Adj Channel Power Ratio (ACPR) – Requirement

Driven by Architecture Decimation and Interpolation Ratios – Driven by Standards and Internal

implementation

Need to add more carriers Availability of Multi-Carrier Power Amplifier Higher capacity channel cards

Higher Data rates over the back plane

© 2002®

Interpolation

Interpolation

RRC Filter

RRC Filter

RRC FilterResampler Decimation


NCO

QQ

ADC

DACTo

Ant

From

Ant

To ChannelCard(LVDS w/CDR)

Inp

ut

Fm

t&

G

ain

Cn

trl

FromCh.Card(LVDS w/CDR)

NCO

RF CardRF Card

II

II

QQ

DelayMatching

TableAddress

Calc(I2 +Q2)1/2

LUT(I & Q)

Compare &Estimate

R S

AdaptiveEst.

I & QDemodFFT

Loop Delay Est

FromPA

FromPA

© 2002®





Conclusion

© 2002®

DelayMatching

LUT(I & Q)

~100 entries12 bit Wordlength

TableAddress

Calc(I2 +Q2)1/2

I

Q

Compare &Estimate

R SI & Q

DemodulatorFFT

Adaptive Est.

Loop DelayEstimator

Embedded Processor

Altera MegaCore IP

To DUCTo DUC

IQ

--I

Q

Altera Solution for DPDAltera Solution for DPD

© 2002®

Optional FIFO, Memory, Other Logic

Nios Processor

Integer Mult /Complex Mult

ExampleALU Only

ALU +

Intgr Mult

ALU + Cmplx Mult

Loop Time (us)

11.190 0.560 0.011

Loop Clocks

1119 56 1.1

MUL Clocks 253 3 -

Complex Mults per Second

89K 1.8M 90.9M

Loop Time = Execution of a single complex multiplyLoop Clocks = Number of clocks to execute single iterationMUL Clocks = Number of clocks to execute the MUL only

Custom Instruction ExampleCustom Instruction Example

Hardware Accelerator

x 50

© 2002®

FlowFlow

AddressCalculation

DDCDDC

FFTFFT

DelayMatching

DelayMatching

(.)__

Gain

(.)__

GainVerrorVerror

= tan-1 (.)

Sn+1=Sn-*escale

Rn+1=Rn-*erotate

Sn+1=Sn-*escale

Rn+1=Rn-*erotate

I1 Q1

In Qn

.. ..

I1 Q1

In Qn

.. ..

I/P toDPDI/P toDPD

FromPA

FromPA

UpdateLUT

UpdateLUT

Loop DelayMeas

Loop DelayMeas

H/W Accelerator

H/W Accelerator

CmplxMult

CmplxMult

ProgrammableLogic

Implementation

ProgrammableLogic

Implementation

Software Implementation(Nios)

Software Implementation(Nios)

© 2002®

Interpolation

Interpolation

RRC Filter

RRC Filter

RRC Filter Decimation


NCO

Q

To

Ant

From

Ant

To ChannelCard(LVDS w/CDR)

Inp

ut

Fm

t&

G

ain

Cn

trl

FromCh.Card(LVDS w/CDR)

NCO

RF Card – Comprehensive Solution

I

I

Q

DelayMatching

TableAddress

Calc(I2 +Q2)1/2

LUT(I & Q)

Compare &Estimate

R S

AdaptiveEst.

I & QDemodFFT

Loop Delay Est

FromPAArctan

Resampler

Altera MegaCore IPStratix Tri-MatrixStratix MAC Block

H/W Accelerator

© 2002®

Advantages of Using FPGAAdvantages of Using FPGA Greater Flexibility

Filter specification based on ACPR requirements Optimal filter architecture for most efficient implementation Support multi-mode capability

Implement Optimal Number of Carriers and Standards

Higher levels of integration Integration of DPD, Digital IF and Transceivers Saving board space Cost savings

Cost Effective Solution Sub $40 in FPGA; Sub-$20 in HardCopy

Speed and size improvements in FPGA can be easily leveraged to support more channels

© 2002®

ConclusionConclusion

RF portion of base-station going through revision

Digital Predistortion Linearizer is a key

functionality being added

FPGA implementation offer significant advantage

over ASSP implementation

Altera Offers comprehensive solution including

devices, tools and IP

Documents

© 2002 ® Wireless Solution Update Asif Batada Marketing Manager, Wireless Business Unit Asif Batada Marketing Manager, Wireless Business Unit