11 EDAEDA

VHDLFPGA/CPLDFPGA/CPLDFPGA/CPLD12311.1 EDA VHDLSYNPLIFYFPGAEXPRESSFPGA COMPILERIILEONARDO

VHDL11-1 EDA

VHDLFPGA/CPLDFPGA/CPLDFPGA/CPLD12311.1 EDA VHDLSYNPLIFYFPGAEXPRESSFPGA COMPILERIILEONARDO

VHDL11-1 EDA

11.2 SynplifyMAX+plusII 11-2 Synplify Pro1.

Tcl

11.2 SynplifyMAX+plusII 11-3 Synplify 1.

3. 4. 5. 2. 11.2 SynplifyMAX+plusII

11-1library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 is port (d : in std_logic_vector (3 downto 0); ld, ce, clk, rst : in std_logic; q : out std_logic_vector (3 downto 0));end cnt4;architecture behave of cnt4 is signal count : std_logic_vector (3 downto 0);beginprocess (clk, rst) begin if rst = '1' then count '0'); elsif rising_edge(clk) then if ld = '1' then count