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מבנה מחשבים1הרצאה
מחשבים מבנה
Lecture 1
Course Introduction
Eytan Ruppin and Alon SchclarSlides from
Randy H. Katz, John Wawrzynek and Dan GarciaBerkeley
2 שקף1הרצאה
Lecture Overview Introduction : Computer Architecture
Administrative Matters
Engineering:
במחשב בסיסיות בינריות פעולות ועד וחשמל ממוליכים
• חשמלי מתח
מוליכים•
• למחצה: מוליך סיליקון
טרנזיסטור•
• אלקטרוניים ברכיבים בינריות פעולות
3 שקף1הרצאה
What is “Computer Architecture”?Computer Architecture =
Instruction Set Architecture +
Machine Organization + …
ארכיטקטורה + = הנדסה
4 שקף1הרצאה
The Instruction Set: a Critical Interface
instruction set
software
hardware
5 שקף1הרצאה
מבנה מחשבים
What are “Machine Structures”?
* Coordination of many
levels (layers) of abstraction
I/O systemProcessor
CompilerOperating
System(Linux, Win, ..)
Application (ex: browser)
Digital DesignCircuit Design
Instruction Set Architecture
Datapath & Control
transistors
MemoryHardware
Software Assembler
6 שקף1הרצאה
Levels of Representation
High Level Language Program
Assembly Language Program
Machine Language Program
Control Signal Specification
Compiler
Assembler
Machine Interpretation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw$15, 0($2)lw$16, 4($2)sw $16,
0($2)sw $15,
4($2)0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
°°
ALUOP[0:3] <= InstReg[9:11] & MASK
8 שקף1הרצאה
MIPS R3000 Instruction Set Architecture(Summary) Instruction Categories
• Load/Store
• Computational
• Jump and Branch
• Floating Point
- coprocessor
• Memory Management
• Special
R0 - R31
PCHI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
Registers
Q: How many already familiar with MIPS ISA?
9 שקף1הרצאה
Execution Cycle
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status
Deposit results in storage for later use
Determine successor instruction
10 שקף1הרצאה
What is “Computer Architecture”?
Coordination of many levels of abstraction
Under a rapidly changing set of forces
Design, Measurement, and Evaluation
I/O systemInstr. Set Proc.
Compiler
OperatingSystem
Application
Digital DesignCircuit Design
Instruction Set Architecture
Firmware
Datapath & Control
Layout
11 שקף1הרצאה
Anatomy: 5 components of any Computer
Personal Computer
Processor
Computer
Control(“brain”)
Datapath(“brawn”)
Memory
(where programs, data live whenrunning)
Devices
Input
Output
Keyboard, Mouse
Display, Printer
Disk (where programs, data live whennot running)
12 שקף1הרצאה
SO
All computers consist of five components• Processor: (1) datapath and (2) control
• (3) Memory
• (4) Input devices and (5) Output devices
Not all “memory” are created equally• Cache: fast (expensive) memory are placed closer to
the processor
• Main memory: less expensive memory--we can have more
Interfaces are where the problems are - between functional units and between the computer and the outside world
Need to design against constraints of performance, power, area and cost
13 שקף1הרצאה
Organization Capabilities & performance
characteristics of principal functional units
• (e.g., Registers, ALU, Shifters, Logic Units, ...)
Ways in which these components are interconnected
Information flows between components
Logic and means by which suchinformation flow is controlled
Choreography of FUs to realize the ISA
Register Transfer Level (RTL) Description
Logic Designer's View
ISA Level
FUs & Interconnect
14 שקף1הרצאה
Forces on Computer Architecture
ComputerArchitecture
Technology ProgrammingLanguages
OperatingSystems
History
Applications
Cleverness
15 שקף1הרצאה
Computer Architecture’s Changing Definition 1950s to 1960s Computer Architecture Course
• Computer Arithmetic
1970s to mid 1980s Computer Architecture Course
• Instruction Set Design, especially ISA appropriate for compilers
1990s Computer Architecture Course• Design of CPU, memory system, I/O system, Multi-
processors, Networks
2000s Computer Architecture Course: • Special purpose architectures, Functionally
reconfigurable, Special considerations for low power/mobile processing
16 שקף1הרצאה
Technology Trends: Memory Capacity(Single-Chip DRAM)
size
Year
Bits
1000
10000
100000
1000000
10000000
100000000
1000000000
1970 1975 1980 1985 1990 1995 2000
year size (Mbit)
1980 0.0625
1983 0.25
1986 1
1989 4
1992 16
1996 64
1998 128
2000 256
2002 512• Now 1.4X/yr, or 2X every 2 years.• 8000X since 1980!
17 שקף1הרצאה Year
Transistors
1000
10000
100000
1000000
10000000
100000000
1970 1975 1980 1985 1990 1995 2000
i80386
i4004
i8080
Pentium
i80486
i80286
i8086
Technology Trends: Microprocessor Complexity
2X transistors/ChipEvery 1.5 years
Called “Moore’s Law”
Alpha 21264: 15 millionPentium Pro: 5.5 millionPowerPC 620: 6.9 millionAlpha 21164: 9.3 millionSparc Ultra: 5.2 million
Moore’s Law
Athlon (K7): 22 Million
Itanium 2: 410 Million
18 שקף1הרצאה
Technology Trends Imply Dramatic Change Processor
• Logic capacity: about 30% per year
• Clock rate: about 20% per year
Memory• DRAM capacity: about 60% per year (4x every 3
years)
• Memory speed: about 10% per year
• Cost per bit: improves about 25% per year
Disk• Capacity: about 60% per year
• Total data use: 100% per 9 months!
Network Bandwidth• Bandwidth increasing more than 100% per year!
19 שקף1הרצאה
Performance Trends
Microprocessors
Minicomputers
MainframesSupercomputers
1995
Year
19901970 1975 1980 1985
Lo
g o
f P
erfo
rma
nce
20 שקף1הרצאה
Course Administration
Instructors:
Eytan Ruppin ([email protected])
TAs: Alon Schcalar ([email protected])
Materials: http://www.cs.tau.ac.il/~ruppin
Books:
1. V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization. McGraw-Hill, 1982
2. H. Taub Digital Circuits and Microporcessors. McGraw-Hill 1982
3. Hennessy and Patterson, Computer Organization Design, the hardware/software interface, Morgan Kaufman 1998
21 שקף1הרצאה
Course ContentComputer Architecture and Engineering
Instruction Set Design Computer Organization
Interfaces Hardware Components
Compiler/System View Logic Designer’s View
“Building Architect” “Construction Engineer”
22 שקף1הרצאה
Grading ציון:
סופי 80%מבחן
20%תרגילים
תרגילים 8
23 שקף1הרצאה
Where are We Going??
מבנהמחשבים
µProc60%/yr.(2X/1.5yr)
DRAM9%/yr.(2X/10 yrs)
1
10
100
1000
198
0 198
1 198
3 198
4 198
5 198
6 198
7 198
8 198
9 199
0 199
1 199
2 199
3 199
4 199
5 199
6 199
7 199
8 199
9 200
0
DRAM
CPU
198
2
Processor-MemoryPerformance Gap:(grows 50% / year)
Per
form
ance
Time
“Moore’s Law”
34-b it A LU
LO register(16x2 bits)
Load
HI
Cle
arH
I
Load
LO
M ultiplicandRegister
S h iftA ll
LoadM p
Extra
2 bits
3 232
LO [1 :0 ]
Result[H I] Result[LO]
32 32
Prev
LO[1]
Booth
Encoder E N C [0 ]
E N C [2 ]
"LO
[0]"
Con trolLog ic
InputM ultiplier
32
S ub /A dd
2
34
34
32
InputM ultiplicand
32=>34sig nEx
34
34x2 M U X
32=>34sig nEx
<<13 4
E N C [1 ]
M ulti x2 /x1
2
2HI register(16x2 bits)
2
01
3 4 Arithmetic
Single/multicycleDatapaths
IFetchDcd Exec Mem WB
IFetchDcd Exec Mem WB
IFetchDcd Exec Mem WB
IFetchDcd Exec Mem WB
Pipelining
Memory Systems
I/O