Impact of modelisation pixel size on OPC consistency

Franck Foussadier1, Emek Yesilada1, Jean-Christophe Le Denmat1, Yorick Trouiller2, Vincent Farys1, Frédéric Robert1, Gurwan Kerrien1, Christian Gardin1, Loic Perraud2,

Florent Vautrin1, Alexandre Villaret1, Catherine Martinelli1, Jonathan Planchot1, Jean Luc Di-Maria2, Mazen Saied1, Mame Kouna Top1

1STMicroelectronics, Crolles, France

2CEA/Leti, Grenoble, France

ABSTRACT In advanced technology nodes, due to accuracy and computing time constraint, OPC has shifted from discrete simulation to pixel based simulation. The simulation is grid based and then interpolation occurs between grid points. Even if the sampling is done below Nyquist rate, interpolation can cause some variations for same polygon placed at different location in the layout. Any variation is rounded during OPC treatment, because of discrete numbers used in OPC output file. The end result is inconsistency in post-OPC layout, where the same input polygon will give different outputs, depending on its position and orientation relative to the grid. This can have a major impact in CD control, in structures like SRAM for example, where mismatching between gates can cause major issue. There are some workarounds to minimize this effect, but most of them are post-treatment fix. In this paper, we will try to identify and solve the root cause of the problem. We will study the relationship between the pixel size and the consistency of post OPC results. The pixel size is often set based on optical parameters, but it might be possible to optimize it around this value to avoid inconsistency. One can say that the optimization will highly depend on design and not be possible for a real layout. As the range of pitch used in a design tends to decrease, thanks to fix pitch layouts, we may optimize pixel size for a full layout. Keywords: OPC, pixel based, snapping

1. INTRODUCTION Until couple years ago, model based OPC was using discrete model. Recently, pixel based simulation for OPC was introduced. It means that the simulation is not done fragment by fragment any more but only once for whole chip. The main advantage being accuracy and run time efficiency when the edge density increases [1,2]. As seen in Figure 1, one of the big difference between both modes is the local approach for discrete versus a global approach for pixel based.

Discrete simulation Pixel based simulation Figure 1: Discrete versus pixel based simulation

Optical Microlithography XXII, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 7274,727416 · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.814047

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Discrete simulation uses sites, located on each fragment. The simulation is done on each site, taking into account only the part of the layout inside the optical diameter. If 2 fragments are identical and have the same surrounding area within the optical diameter, they will have the same simulation. It will induce the same correction after OPC. As the simulation time is roughly proportional to the number of sites, going to advanced technology nodes implies higher density of sites and strong increase in run time. To avoid such problems, pixel based simulation was introduced. Pixel based simulation is done globally. The whole chip is converted to a grey scale image using pixel grid. This image uses pixel which sampling should be done below Nyquist rate, defined by formula (1). The idea of Nyquist rate is to be able to reproduce the optical system behavior with a good fidelity, without over sampling.

)1(4 σ

λ+

=NA

Nyquist (1)

This value is completely adapted to optical imaging. Nevertheless the polygons simulated have their own design grid which is not the same one than the one used for simulation. Let’s look closely to what happened to simulation. Figure 2 shows the different stage of a pixel based simulation.

Simulated Polygon

Pixel based image

Interpolated image

Resist contour

Simulated Polygon

Pixel based image

Interpolated image

Resist contour

Figure 2: Different steps of pixel based image

The polygon is simulated based on grid. The aerial image shows steps corresponding to the size of the pixel. This aerial image is then smoothed using interpolation. Finally the resist contour is calculated based on this interpolated image. The resist contour is symmetrical compared to the initial polygon and the asymmetry present in the pixel aerial image is not seen. Unfortunately, this ideal case is not fully transpose in OPC output. Sometimes, the OPC output is not consistent and gets “history” of the pixel based approach, despite the smoothing steps. Figure 3 shows an example of this effect.

50 50 51 50

45 45 45 45

OPC input

OPC output

50 50 51 50

45 45 45 45

OPC input

OPC output

Figure 3: OPC output inconsistency

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A 1D array with a zero range between the lines gives as output a range of couple DBU (database unit). The root cause is most probably rounding effects occurring while converting floating point value coming from ideal OPC to discrete value needed for outputting a file based on DBU. There are 3 major impacts of this inconsistency. First, the CD uniformity is increased. This is critical for advanced technology nodes, where the budget is very tight. Second, the SRAM matching for gate is impacted, especially if one line out of two is different. Third, the OPC verification becomes difficult. Identical input gives different output. It is difficult to know if the correct OPC was applied and if there was no issue in the OPC flow. This inconsistency can be reduced by different tricks proposed by OPC vendors. But the tricks are addressing the problem after the aerial image simulation. No one is working directly on the root cause. How can we quantify and minimize this inconsistency?

2. OPC INCONSISTENCY METRICS For easiness of study, we will focus only on 1D structure. A specific test case was created. As shown in Figure 4, the test case was composed by a minimum of 200 lines plus at least 2 times the optical diameter on each side. The lines were at least 5 times the optical diameter long. This test case was duplicated, varying width and pitch over a large range.

>5 OD

>2 OD >2 OD

>200 lines

CD Variance calculated

>5 OD

>2 OD >2 OD

>200 lines

>5 OD

>2 OD >2 OD

>200 lines

CD Variance calculatedCD Variance calculated Figure 4: 1D test case example, for a given CD and pitch

OPC was processed on this test case. No MRC constraint was applied but the output grid was kept to production value. Different layers were processed, using different model types and different OPC software. The center part was then used to calculate OPC output CD variance. A normalization of post OPC CD value was done and the variance was calculated per pitch taking into account different widths and per width taking into account different pitches.

3. OPC VARIANCE VERSUS PITCH AND WIDTH Figure 5, 6 and 7 shows the OPC output variance for 3 different layers. The plots represent variance versus pitch in dark colour and variance versus width in light colour. One important point to notice is that almost no variance=0 is observed. There is a very noisy behaviour going for local minima to maxima almost randomly. This noisy behaviour is more visible on layer B, but present on all layers.

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pitch & width

OP

C o

utpu

t var

ianc

e

variance vs pitch variance vs width

Layer A

Variance x4

Figure 5: Variance versus pitch and width for layer A

pitch & width

OP

C o

utpu

t var

ianc

e

variance vs pitch variance vs width

Layer B

Variance x4

Figure 6: Variance versus pitch and width for layer B

pitch & width

OP

C o

utpu

t var

ianc

e

variance vs pitch variance vs width

Layer C

Variance x4

Figure 7: Variance versus pitch and width for layer C

Looking more carefully, we can identify a pseudo period on local minima, especially for variance versus pitch. This is more visible on layer A and layer C, but present as well on layer B. On all cases, there is roughly a factor 4 between the local minima and the local maxima.

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A factor 4 in variance has 2 different meanings. If the spike frequency is the same, a factor 4 in variance means a factor 2 in mask CD range. For example, if a 1 nm CD variation, as shown in Figure 3, is a maximum of variance, a minimum of variance would be 0.5 nm CD variation. Talking about wafer CD, as the MEEF applies the same way in both cases, we will find the factor 2 in CD variation. In our example, with a MEEF of 2 for example, a maximum will be 2 nm CD variation and the minimum will be 1 nm CD variation. If we consider now that the spike range is the same, then a factor 4 means a high increase in spike frequency. Depending on the frequency of the minima, the frequency of the maxima will be between 4 and 8 times higher. How to minimize this variance?

4. PIXEL SIZE INFLUENCE The calculation done above for variance versus pitch was repeated for different simulation pixel size. Figure 8 shows a map of variance versus pixel and pitch. The dark blue points represent location where the variance is low and the dark red point represent location where the variance is high.

pitch = n * pixel / 8

k1 = 0.2

Figure 8: Variance map versus pixel and pitch

On the bottom region of the map, the pitch is small. We are close to the optical limit of the system. The NA (numerical aperture) used in the model is not big enough for the pitch used. The aerial image has low contrast and no relevant resist contour is calculated. If we transfer pitch to k1 factor using the formula (2) we are in a region where k1 is aournd or below 0.2.

NA

kpitch λ12= (2)

OPC tries to find mask that would gives an output but without getting to a convergence point. This leads to fuzzy output and the variance is high.

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On the right side of the map the pixel is big. We are close or above Nyquist frequency. The sampling rate is not sufficient to capture the optical effect of the system. The aerial image calculated is not accurate. It is not possible to find a convergence point. As for the small pitch region, we have fuzzy output and a high variance. On the upper left part of the map, the pixel is small and the pitch is big. We are close to continuous simulation. The grid effect is very small and then the variance is low. The disadvantage of this region is that a small pixel requires longer calculation time for a given layout. Due to productivity constraint, we can not afford to have production OPC running in this pixel and pitch configuration. The middle region represents the working zone for OPC. There is a continuous trend going from low variance where the pitch/pixel ratio is high, to high variance where the pitch/pixel ratio is low. Added to this global trend we can see highs and lows. The black lines superposed to the map represent locations where pitch is a multiple of pixel/8. We can see that all the local minima are located on these lines. This is a clear indication that the pixel based approach, even with a smoothing step, doesn’t succeed to get ride of all grid effects. We can notice as well vertical or horizontal lines which are noticeable lower or higher than the surrounding area. These lines are artifacts. The low point corresponds to value that are easily dividable like multiple of 10 for example. The high points correspond to value difficult to divide, like prime numbers for example. After focusing on variance versus pitch and pixel, let’s see now variance versus width and pixel. Figure 9 shows a map of variance versus pixel and width

Figure 9: Variance map versus pixel and width

We can find commonalities for the variance map versus pixel and pitch. On the bottom region of the map, the width is small. Like for the pitch, the NA used in the model is not big enough to image features that small. No convergence is found we have fuzzy output, the variance is high. On the right region of the map the pixel is big. We are close or above Nyquist frequency. The sampling rate is not sufficient and as for the pitch it is not possible to find a convergence point. We have fuzzy output and a high variance. Except these similarities with the pixel pitch map, the remaining regions behave differently for width than for pitch. There is no width-pixel cross effect. The left region corresponding to small pixel gets low variance. As the pixel size

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increase, the variance increase continuously. It just means that with smaller pixel, the simulation is more continuous and more accurate. Few artefacts are seen where pixel is at a noticeable value. We have columns of lower value where pixel is easily dividable, like multiple of 10 for example. The other way around, we have columns of higher value where pixel can’t be easily divided, like prime number for example.

5. REAL LAYOUT APPLICATION This study was done using 1D test case, but what about real 2D layout? Having similar study done with 2D would be very difficult, requiring huge test case to have similar number of data and get statistical analysis. In a 1D test case, every measurement point is separated by only a couple of hundreds nm. In a 2D test case, a standard cell is couple micron wide. The run time needed and the size of the file will completely explode if we want to have similar maps done with 2D layout, with enough statistical data. Moreover, it is not easy to say that the study done in 1D can be extrapolated without adjustment in 2D. But few facts make this study usable anyway. First, and as seen previously, the variance can have a major impact on SRAM, where gate CD mismatching can be a major yield detractor. SRAM tends to be very close to 1D array for gate. Applying the correct pixel on this array can minimize the risk of having unmatched gates on SRAM. Second, on advanced technology nodes, fix pitch is more and more used. It means that for the most critical dimension, only 1 or a couple of pitches are allowed. This is particularly used for gates. This was introduced to minimize CD variation. In that case, its worth to choose a pixel that will minimize OPC variance as well and avoid creating a source of CD variation. Third, on memory cell, we have by definition an array of repetitive structure. Even if the exact pitch of each layer is different from the array step, applying a pixel that have a proper proportionality will help good matching between cells. Based on these 3 facts, we can say that this study is applicable on advanced technology nodes and can help to minimize the OPC variance.

6. CONCLUSION We demonstrated in this paper that pixel based OPC, despite a lot of advantages, has some inconsistency in output. This inconsistency is coming mainly from the mismatch between the design grid and the simulation grid, creating an aliasing effect. We find a way to measure this inconsistency. Predictable effects were confirmed. We have high variance coming from fuzzy OPC when the pixel size is close or above Nyquist rate. We have the same effect when the feature we want to apply OPC on is too small for the NA of the optical system. Finally, we find a way to minimize this effect while keeping the run time in an acceptable value. The pixel used should be chosen so that the most frequent pitch is a multiple of pixel/8. During the setup of a technology node, the pitches used are defined early. But when it is time to calibrate OPC models and run OPC on products, slightly adjusting the pixel will help to minimize spikes in OPC output.

REFERENCES 1. Y. Cao, Y.-W. Lu, L. Chen, J. Ye, “Optimized hardware and software for fast full-chip simulation” Proc. SPIE vol.

5754, Optical Microlithography XVIII (2004) 2. N. Cobb, Y. Granik “Dense OPC for 65nm and below” Proc. SPIE vol. 5992, 25th Annual BACUS Symposium on

Photomask Technology (2005)

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