Step-by-Step Approach to AC Line-Powered Converters

Power Supply Design Seminar

Topic Categories:Design Reviews – Full Power Supply

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Reproduced from2004 Texas Instruments Power Supply Design Seminar

SEM1600, Topic 3TI Literature Number: SLUP229

© 2004, 2011 Texas Instruments Incorporated

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Design Review: A Step-By-Step Approach to AC

Line-Powered Converters

TexasInstruments 1 SLUP229

Anoffline,three-output,150-Wforwardconverterisusedasanexampletoillustratethedesignprocessfor typical isolated converters. This example emphasizes the basics with a double-ended forwardtopologyusingcoupledinductorsforoutputaccuracy.Designissuesandtrade-offdecisionstooptimizepower efficiency while keeping costs to a minimum are highlighted. Finally, the presentation ofmeasuredperformanceresultsconfirmsthedesignprocess.

A. Defining Requirements

LoadConcerns•

• •

• • •

PowerTrainConcerns•

• • •


B. Defining the Topology

C. Defining the Input Configuration

• • • • • • •

×RMSV


C1

C2

CINSwitchingRegulator

Input230 V AC, 50 Hz120 V AC, 60 Hz

220 V

110 V

VC1

VC2

VBULK

Fig. 1. A voltage doubling input range switchconfiguration.

D. Transformer Design

E. Voltage-Mode or Current- Mode Control

F. Output Filter Design


A. Defining the Requirements (Plan of Record)

•

•

•

•

• •

• • ≥ •

• •

• • •

B. Defining the Topology and Control Method

automatically

ΩΩΩΩ


C1

C2

CIN

D2

D1Q1

Q2

NP

D3

D4COUT

L

VOUT

VBULK

T2

NS

NA

Fig.2.Two-SwitchForwardConverter

C. Defining the Input Section VoltageDoublervs.Full-WaveBridgeInput

VVDutyVV OUT

SEC

===

peakVVV RMSDC =×=

peakVVV RMSDC =×=

requireddiodeVderatingwithV

VVV

V SECDC

DCSEC

×=

×=×=

peakVVV RMSDC =××=

peakVVV RMSDC =××=

peakVVDC =×=

peakVVV RMSDC =×=


requiredisdiodeVaonlyderatingwith

VVVVV

V SECDC

DCSEC

×

=×=×=

•

•

•

•

InputCapacitors

T

tC

VPKVMIN

tR

CapacitorVoltage

CapacitorCurrent

ICHARGE

Fig.3.InputCapacitorWaveforms

WWPP OUTIN

==×= η

JoulesHz

W

f

P

fPW

OUT

LINE

OUT

LINE

ININ

=

=

==η

( ) ( )[ ]MINPK

ININ VV

WC−

=

veconservatibetouseVV

VV RMSVPK

=×−=

×=

Vveconservatibetorippleuse

VVVV RIPPLEVPKVMIN

=

×=−=

( ) ( )[ ] ( ) ( )F

VVWC

MINPK

ININ

µ

=−

=−

=

µ


JoulesHz

W

fPWLINE

ININ

=

==

( ) ( )[ ]

−==

CCPK VV

WCC

•

•

veconservatibetouseVV

VV RMSVCPK

=×−=

×=′

( ) ( ) VVVV CPKMINC

=−×=′−

=

( ) ( )[ ]

( ) ( )[ ] FJ

VVWCC

CCPK

µ

=

−=

−′==

µ

Ω, Ω, Ω

D. Transformer Turns Ratio

SecondaryTurns

NN

VV =


PrimaryTurns

[ ] linehighatturnsTV

VN INP

===

[ ] linelowatturnsTV

VN INP

===

Unitrode MagneticsDesign Handbook


• •

• Ω •

Ω • Ω

• • •

230 V to 375 V(input)

4

3

15

6

7

9 3.3 V

10

8 5 V

12 V @ 3.0 V

12 V @ 0.1 A(bias)

Fig.4.Transformerschematic.

E. Output Inductor

coupledinductor, steered adjusted

AII MINPP =×=−

didtVL ×=

• •

•

S

P

IN

OUT

NN

VVCycleDuty ×=

( )

×−=

SWMINOFF f

Dt

=

×

=CycleDuty

• µ • µ

HuseHA

sdidtVL µµµ

=×

=×=


µ

6

7

(5 V)9.3 µµµµH

9

10

(3.3 V)4.14 µµµµH

(12 V)50 µµµµH

2,1

5,4

Fig.5.Inductorschematic.

F. Output Capacitors

CapacitorEquivalentSeriesResistance(ESR)

OUT

ESRRIPPLERIPPLE V

RIV ×=

outputVmAmV

IV

RppMIN

OUTESR

Ω=

==−

outputVmAmVRESR Ω==

outputVmAmVRESR Ω==

µµµµ ΩΩΩΩ


CapacitorValue

∆

dtCIdV ×∆=

dVdtIC ×∆=

( )( ) mVVV

VVVdV SETPOINTOUTOUT

==−=−=

µ µ

∆

FsAdVdtIC µµ

=×=×∆=

( )( ) mVVV


==−=−=

FV

sAC µµ =×=

( )( ) mVVV


==−=−=

FVsAC µµ

=×=

µ RMSRippleCurrent

PEAK

RMSII =

AAIRMS

==

AAIRMS

==

mAAI RMS

==


FinalSelection µ

Ω

µ Ω

µ Ω

µ Ω

µ µ

G. Output Rectifier Snubbers

LCf

π=

LCRQ =

LCLCQR ==

SWfVCP =

Ω,

H. Output Rectifiers

µµµµ

Ω)Ω)Ω)Ω)

µµµµ

Ω)Ω)Ω)Ω)


≅×==P

SPKR N

NVV

≅×==P

SPKR N

NVV

AAAIII peakRIPPLEOUTDIODE =+=+=



CycleDutyVIP FPEAKAVG ×+=

PEAKFDIODE IVP ×=

I. Power Switching FETs

Ω

Design andApplicationGuideforHighSpeedMOSFETGateDrive Circuits

µ


+VDRV - VCVCC

OUT

GND

R5

+VDRV

0 V

- VC

VC - VD+ - - +

C5 C9D5 R10

+VDRV - VD

- VD

VDRV

Fig.6.Isolatedgatedrivetransformer.

J. IC PWM Controller

•

• • • • • • PWMBiasSupplyandVCCCapacitance

•

• µ

•

0.1

0

0.2

0.3

0.4

0.5

OFF ON

TurnOn

TurnOff

VCC - Supply Voltage - V

I IN -

Supp

ly C

urre

nt -

mA

Fig.7.Inputvoltage(VCC)hysteresiswindow


•

• µ start-upcurrent

mAk

VV

ICLAMP

DC

=

Ω

−

=

•

• operatingsupplycurrent

mAkHznCQgFI =×==

mAmAmAIII FETdriveMAXTOTAL

=+=+=

•

FFdVdtIC µµ

≅=×=×∆=

µ µ

µΗ µ

Ω

PrimaryCurrentSenseResistor


C1

C2

220 V

110 V

VC1

VC2

VBULK

39 kΩΩΩΩ

43 kΩΩΩΩ

VCCGND

0.1 µµµµF 47 µµµµF 12 V

200 ΩΩΩΩ

2.2 µµµµF

L

+

- UCC3813

To Power Stage

Fig.8.PWMstart-upandbiascurrent.

A

outputeachforNN

II

whereNN

III

P

SPEAKS

P

SSMAGP

=

+

+

=

=′

′+=

( ) ( )

A

smH

tL

VI ON

INMAG

=

=

= µ

AAAIII SMAGP =+=′+=

Ω=== AV

IV

RS

SS

Ω

K. Setting Up the Loop

current source only,

µ


µ µ Ω Ω

µ µ

( ) Ω=−−=

A

VVVR

Ω==

mAVR

1 5-VVOUT

4

Q34N36

2

5

6 R17750 ΩΩΩΩ C24

TBD

C22TBD

R19TBD

R2010 kΩΩΩΩ

R2110 kΩΩΩΩ

R22OPEN

3.3-VVOUT

R16200 ΩΩΩΩ

C262.2 µµµµF

R1810 kΩΩΩΩ

12-VVOUT

8

1UCC3813-1

R7150 ΩΩΩΩ

FB

U2

TL431A

2+

REF

COMP

R6OPEN

REF D1210 V

Fig.9.Isolatedpowersupplyloopclosed.


ClosingtheLoop

µ

L. A Few Optional Ideas

•

•

•

•

supervisorycircuits

• Ω

A. Efficiency


+

++

+

+

+

++

32C

TQ03

0

Fig10.Forwardconverterschematic.


0.77

0.76

0.78

0.79

0.81

0.82Ef

ficie

ncy

- %

0.78

0.80

1.0 1.5 2.0 2.5 3.0 3.5 4.0

144 W

106 W

25 W

Fig.11.Efficiency.

B. Cross Regulation

•

•

• • •

2

0

6

8

12

14

V OU

T - O

utpu

t Vol

tage

- V

4

10

3.49

4.96

12.96

Output Loading

11.44

4.95

3.11

5 V Max3.3 V, 12 V Min

5 V Min

3.3 V, 12 V Max

Fig.12.Crossregulationextremes.

C. Input Capacitor Ripple

µ

µ


t - Time - 2.5 ms / div

Bulk Capacitor Voltage(50 V/div)

Fig. 13.Bulk capacitor input ripple at 90-VAC,maximumload.

D. Primary Waveforms

µ

µ µ

Q1 Drain Voltage (100 V/div)

Q1 Drain Current (2 A/div)

t - Time - 2.5 µµµµs/div Fig. 14. Q1 drain-to-source voltage and draincurrentatmaximumloadand90-VACinput.

µ µ

Q1Drain Voltage

(100 V/div)

Q1Drain Current

(2 A/div)

t - Time - 2.5 µµµµs/div Fig.15.Q1drain-to-soucevoltageatmaximumloadand264VACinput.


E. Output Ripple Voltage

t - Time - 5 µµµµs/div

12-V Ripple Voltage (50 mV/div)

Fig.16.12-VRipplevoltage.


5-V Ripple Voltage (10 mV/div)

Fig.17.5-VRippleVoltage.


3.3-V Ripple Voltage (50 mV/div)

Fig.18.3.3-VRipplevoltage.


F. Diode Voltage

t - Time - 2.5 µµµµs/div

5-V Diode Input Voltage (10 V/div)

Fig.19.Diodeblockingvoltage.

UnitrodeMagneticsDesignHandbookTopicR5

ApplicationNote

UnitrodePowerSupplyDesignSeminarSEM-100SectionI1

ApplicationNote

ApplicationNote

TIPowerSupplyDesignSeminarSEM-1500,Topic

TI Power Supply DesignSeminarSEM-1400

(SLUP132)

(SLUP204)

(SLUP169)


Fig.20.DesignPCB

µ

µ

µ µ µ µ

µ

µ

µ Ω


µ Ω

Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω

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Step-by-Step Approach to AC Line-Powered Converters