Digital Integrated Circuits

© Digital Integrated Circuits2ndSequential Circuits

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

November 2002


Sequential LogicSequential Logic

2 storage mechanisms• positive feedback• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs


Naming ConventionsNaming Conventions

In our text:a latch is level sensitivea register is edge-triggered

There are many different naming conventions

For instance, many books call edge-triggered elements flip-flopsThis leads to confusion however


Latch versus RegisterLatch versus RegisterLatchstores data when clock is low

D

Clk

Q D

Clk

Q

Registerstores data when clock rises

Clk Clk

D D

Q Q


LatchesLatches

In

clk

In

Out

Positive Latch

CLK

DG

Q

Out

Outstable

Outfollows In

In

clk

In

Out

Negative Latch

CLK

DG

Q

Out

Outstable

Outfollows In


LatchLatch--Based DesignBased Design

N latch is transparentwhen φ = 0

P latch is transparent when φ = 1

PLatch Logic

Logic

NLatch

φ


Timing DefinitionsTiming Definitions

t

CLK

t

D

tc 2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q


Characterizing TimingCharacterizing Timing

Clk

D Q

tC 2 Q

Clk

D Q

tC 2 Q

tD 2 Q

Register Latch


Maximum Clock FrequencyMaximum Clock Frequency

FF’s

LOGIC

tp,comb

φ

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delay

tclk-Q + tp,comb + tsetup = T


Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1 Vo2

Vo2 = Vi 1

Vo1 = Vi 2

V

o

1

V

i

2

5

V

o

1

V

i

2

5

V

o

1

Vi1

A

C

B

Vo2

Vi1 = Vo2

Vo1 Vi2

Vi2 = Vo1


MetaMeta--StabilityStability

Gain should be larger than 1 in the transition region

A

C

d

B

Vi2

5V

o1

Vi1 5 Vo2

A

C

d

B

Vi2

5V

o1

Vi1 5 Vo2


MuxMux--Based LatchesBased LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ ⋅+⋅=InClkQClkQ ⋅+⋅=


MuxMux--Based LatchBased Latch

CLK

CLK

CLK

D

Q


Writing into a Static LatchWriting into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states


MuxMux--Based LatchBased Latch

CLK

CLK

CLK

CLK

QM

QM

NMOS only Non-overlapping clocks


MasterMaster--Slave (EdgeSlave (Edge--Triggered) Triggered) RegisterRegister

1

0D

CLK

QM

Master

0

1

CLK

Q

Slave

QM

Q

D

CLK

Two opposite latches trigger on edgeAlso called master-slave latch pair


MasterMaster--Slave RegisterSlave Register

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexer-based latch pair


ClkClk--Q DelayQ Delay

D

Q

CLK

2 0.5

0.5

1.5

2.5

tc 2 q(lh)

0.5 1 1.5 2 2.50time, nsec

Vol

ts

tc 2 q(hl)


Setup TimeSetup Time

D

Q

QM

CLK

I2 2 T2

2 0.5

Vol

ts

0.0

0.2 0.4time (nsec)

(a) Tsetup 5 0.21 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0

DQ

QM

CLK

I2 2 T2

2 0.5V

olts

0.0

0.2 0.4time (nsec)

(b) Tsetup 5 0.20 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0


Reduced Clock Load Reduced Clock Load MasterMaster--Slave RegisterSlave Register

D QT1 I 1

CLK

CLK

T2

CLK

CLKI2

I 3

I4


Avoiding Clock OverlapAvoiding Clock OverlapCLK

CLK

AB

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK


Static CStatic C22MOS registerMOS register




CrossCross--coupled NOR Pair coupled NOR Pair

Forbidden State

S

S

R

QQ

Q

QRS Q

Q00 Q

101 0

010 1011 0R Q

NOR-based set-reset


CrossCross--coupled NAND paircoupled NAND pair

S

QR

Q

Cross-coupled NANDs

Qn-1Qn-11110010110

N/AN/A00QnQnRS


CrossCross--coupled coupled NOR NOR pairpair


SetSet--Reset NOR Reset NOR LatchLatch


CrossCross--coupled coupled NAND NAND pairpair


SetSet--Reset NAND Reset NAND LatchLatch


SetSet--Reset MasterReset Master--Slave Slave RegisterRegister


SetSet--Reset NOR LatchReset NOR Latch

M1

M2

M3

M4

Q

M5S

M6CLK

M7 R

M8 CLK

VDD

Q

This is not used in datapaths any more,but is a basic building memory cell


Sizing IssuesSizing Issues

Output voltage dependenceon transistor width

Transient response

4.03.53.0W/L5 and 6

(a)

2.52.00.0

0.5

1.0

1.5

2.0

Q (V

olts

)

time (ns)

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

W = 1 mµ

3

Volts

Q S

W = 0.9 mµW = 0.8 mµ

W = 0.7 mµW = 0.6 mµ

W = 0.5 mµ


Storage MechanismsStorage Mechanisms

D

CLK

CLK

Q

Dynamic (charge-based)

CLK

CLK

CLK

D

Q

Static


Making a Dynamic Latch PseudoMaking a Dynamic Latch Pseudo--StaticStatic

D

CLK

CLK

D


More Precise Setup TimeMore Precise Setup Time

tD 2 C

t

t

t

tC 2 Q1.05tC 2 Q

tSu

tH

Clk

D

Q

(b)

(a)


Clk-Q Delay

TSetup-1

TClk-Q

Time

Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1


Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1



Clk-Q Delay

TSetup-1

TClk-Q

Time

Timet=0

ClockDataTSetup-1


D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1


Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1



Timet=0

ClockDataTSetup-1

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1


Clk-Q Delay

TSetup-1

TClk-Q

Time


Setup/Hold Time IllustrationsSetup/Hold Time IllustrationsHold-1 case

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

Timet=0

DataClockTHold-1

0

Clk-Q Delay

THold-1

TClk-Q

Time


Clk-Q Delay

THold-1

TClk-Q

Time

Timet=0

DataClockTHold-1


D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

0


Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

Timet=0

DataClockTHold-1


0


Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockTHold-1

Data


0


Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

Q M

CP

D1 SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data


0

⇒


Dynamic Latches/Registers: CDynamic Latches/Registers: C22MOSMOS

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

Slave Stage

“Keepers” can be added to make circuit pseudo-static


Insensitive to ClockInsensitive to Clock--OverlapOverlap

M1

D Q

M4

M2

0 0

VDD

X

M5

M8

M6

VDD

(a) (0-0) overlap

M3

M1

D Q

M2

1

VDD

X

M71

M5

M6

VDD

(b) (1-1) overlap


SingleSingle--phase Latches: TSPCphase Latches: TSPC

CLKIn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Out

Double n-C2MOS Double p-C2MOS


Including Logic in TSPCIncluding Logic in TSPC

CLKIn CLK

VDDVDD

QPUN

PDN

CLK

VDD

Q

CLK

VDD

In1

In1 In2

In2

AND latchExample: logic inside the latch


Simplified TSPC Latches (splitSimplified TSPC Latches (split--output)output)

Split-output n-C2MOS Split-output p-C2MOS


Precharged Precharged Latches (TSPCLatches (TSPC--1)1)

Precharged n-C2MOS latch Precharged p-C2MOS latch


PrechargedPrecharged Latches (TSPCLatches (TSPC--2)2)

Precharged n-C2MOS latch Precharged p-C2MOS latch


PrechargedPrecharged Register (TSPC)Register (TSPC)

CLK

CLK

D

VDD

M3

M2

M1

CLK

Y

VDD

Q

Q

M9

M8

M7

CLK

X

VDD

M6

M5

M4

p-C2MOS – double n-C2MOS



Negative latch – Positive latch


PipeliningPipeliningRE

GRE

G

REGlog

a

CLK

CLK

CLK

Out

b

REG

REG

REGlog

a

CLK

CLK

CLK

REG

CLK

REG

CLK

Out

b

Reference Pipelined


PulsePulse--Triggered LatchesTriggered LatchesAn Alternative ApproachAn Alternative Approach

Master-Slave Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:


Pulsed LatchesPulsed Latches

CLKGD

VDD

M3

M2

M1

CLKG

VDD

M6

Q

M5

M4

CLK

CLKG

VDD

XMP

MN

(a) register (b) glitch generation

CLK

CLKG

(c) glitch clock


Pulsed LatchesPulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

P1

M3

M2D

CLK

M1

P3

M6

Qx

M5

M4

P2

CLKD


Hybrid LatchHybrid Latch--FF TimingFF Timing

20.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.20.0 0.4

QD

time (ns)

Volts

0.6 0.8 1.0

CLKDCLK


In Out

Vin

Vout VOH

VOL

VM– VM+

•VTC with hysteresis

•Restores signal slopes


LatchLatch--Based PipelineBased Pipeline

F G

CLK

CLK

In Out

C1 C2

CLK

C3

CLK

CLK

Compute F compute G


Pseudo Pseudo twotwo--phase clockingphase clocking


Pseudo Pseudo twotwo--phase pipeliningphase pipelining


Pseudo Pseudo twotwo--phase pipeliningphase pipelining


Four Phase ClockingFour Phase Clocking


Four Phase LogicFour Phase Logic


Two phase clocking Two phase clocking (NORA (NORA LogicLogic))


NORA Composition rulesNORA Composition rules

HoldPrechargeEvaluateEvaluateCLK = 1

EvaluateEvaluateHoldPrechargeCLK = 0

LatchLogic LatchLogic

Φ SectionΦ SectionΦ SectionΦ Section__ __


NORA Logic (NORA Logic (ΦΦ SectionSection))



In1In2

In3

Clk

Mp

Mn

In4

In5

Clk

ClkClk

to n-Logic to p-Logic

n-Logic

p-Logic

Out2

Out1

Clk

ClkOut

Mp

Mn


NORA Logic (NORA Logic (ΦΦ SectionSection))____



In1In2

In3

Clk

Mp

Mn

In4

In5

ClkClk

to n-Logic to p-Logic

n-Logic

p-Logic

Out2

Out1

Clk

ClkOut

Clk Mn

Mp

____


Input Input variation variation racerace


NORA Composition rulesNORA Composition rulesInternal races:Only one input transition to a dynamic logic block is allowed from the OFF to the ON condition: hence, no interposition of static gates between dynamic blocks is allowed due to glitching; also, an inverter must be interposed between logic blocks of thesame kind (n → n, or p → p)

External races:Input variation: an even number of static or dynamic inversion stages is required, or a dynamic block must exist preceded by an even number of static or dynamic inversion stages;Precharge: only an even number of static inversion stages are allowed between the last dynamic block and the C2MOS latch.


OneOne--phase logicphase logic ((ΦΦ SectionSection))


OneOne--phase Logic (phase Logic (ΦΦ SectionSection))____


SingleSingle--phasephase SRAMSRAM


Single Single phase phase PLAPLA


One One phase prechargedphase precharged bus systembus system


Precharged Precharged bus bus repeaterrepeater


Noise Noise in in dynamic dynamic CMOS CMOS circuitscircuitsNonNon--precharged precharged n n latcheslatches

CLKIn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Out


Noise Noise in in dynamic dynamic CMOS CMOS circuitscircuitsNonNon--precharged precharged n n LatchesLatches

If the input of a non-precharged n latch rises after the falling edge of the clock, the middle node is dynamic high and the output is dynamic low. A negative glitch on the middle node or a positive glitch on VDD may cause the output to riseIf the input of a non-precharged n latch falls after the falling edge of the clock, the output node is dynamic high. A negative glitch on ground or a positive glitch on the clock signal may cause the output to fallIf the input of a non-precharged n latch rises after the falling edge of the clock, a negative glitch on ground or a postive glitch on the clock may cause the middle node to fall and the output to rise


Noise Noise in in dynamic dynamic CMOS CMOS circuitscircuitsPrecharged Precharged n n LatchesLatches


Noise Noise in in dynamic dynamic CMOS CMOS circuitscircuitsPrecharged Precharged n n LatchesLatches

A positive glitch on a low input of a precharged latch, or a negative glitch on ground when the clock is high (evaluate conditions) may cause the middle node to fall and the output to riseThe output node of a precharged n latch is dynamichigh when the clock is low (precharge and hold). A negative glitch on ground or a positive glitch on the clock signal may cause the output to fall


Domino pipeline Domino pipeline with with ideal ideal clocksclocks


Domino pipeline Domino pipeline with with clock clock skewskew


TwoTwo--phase overlapping phase overlapping domino domino clocksclocks


FourFour--phase phase domino domino clocksclocks


Precharge Precharge time time constraintconstraint


Evaluation Evaluation time time constraintconstraint


Basic Basic skew toleranceskew tolerance


Global skew toleranceGlobal skew tolerance


Time Time borrowingborrowing


Time Time borrowing availabilityborrowing availability


TwoTwo--phase phase clock generationclock generation


FourFour--phase phase clock generationclock generation


Simplified fourSimplified four--phase phase clock clock generationgeneration


Domino/Domino/static interfacesstatic interfaces


SeltSelt--timed timed PLA PLA


ALU selfALU self--bypass bypass pathpathTextbook Textbook dominodomino


ALU selfALU self--bypass bypass pathpathSkewSkew--tolerant tolerant dominodomino


ALU performance ALU performance simulation resultssimulation results


Noise Suppression using Schmitt Noise Suppression using Schmitt TriggerTrigger

Vin

t0

VM−

VM+

t

Vout

t0 + tp t


CMOS Schmitt TriggerCMOS Schmitt Trigger

Moves switching thresholdof the first inverter

Vin

M2

M1

VDD

X Vout

M4

M3


Schmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC

2.5

V

X

(V)

VM2

VM1

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4. The width is k* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

V

x

(V)

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5


CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)

VDD

VDD

OutIn

M1

M5

M2

X

M3

M4

M6


Multivibrator Multivibrator CircuitsCircuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T


TransitionTransition--Triggered Triggered MonostableMonostable

DELAY

td

In

Outtd


MonostableMonostable Trigger (RCTrigger (RC--based)based)VDD

InOutA B

C

R

In

B

Out t

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.


AstableAstable MultivibratorsMultivibrators (Oscillators)(Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

0.0

0.0

0.5

1.0

1.5

2.0

2.5V1 V3 V5

3.0

20.50.5

time (ns)

Vol

ts

1.0 1.5


Relaxation OscillatorRelaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC


Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pH

L (n

sec)

propagation delay as a functionof control voltage


Differential Delay Element and VCODifferential Delay Element and VCO

in2

two stage VCO

v 1

v 2

v 3

v 4

V ctrl

V o2 V o1

in1

delay cell

simulated waveforms of 2-stage VCO

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2 0.51.5

V 1 V 2 V 3 V 4

time (ns)2.5 3.5

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