Chapter 6fixed point arithemetics

Outline

• Addition and Subtraction Introduction, Addition and Subtraction with signed magnitude,Hardware Implementation, Hardware Algorithm Addition and Subtraction with signed 2’s complement

• Multiplication Introduction, Hardware Implementation and Algorithm, Booth Introduction, Hardware Implementation and Algorithm, Boothalgorithm, Array multiplier

• Division Algorithm Introduction, Hardware implementation, Overflow, Hardwarealgorithm, Restoring method, Comparison and non-restoring method

• Computational problem are solved in digital computer by using arithemetic instructions

• Four basic arithemetic operations– Addition– Subtraction– Subtraction– Multiplication– Division

• Every mathematic problem can be formulated using these four basic operations

• In this chapter we develop various arithmetic algorithms and their procedure for hardware implementaion

Integer Representation

We have the smallest possible alphabet: thesymbols 0 & 1 represent everything• No minus sign• No period• No period• Signed-Magnitude• Two’s complement

Benefits of 2’s complement

• One representation of zero• Arithmetic works easily (see later)• Negating is fairly easy— 3 = 00000011— 3 = 00000011— Boolean complement gives 11111100— Add 1 to LSB

Addition and Subtraction

• Already familiar with these operations• Three ways of representation of signed fixed point

number– Signed magnitude– Signed magnitude– Signed 1’s compliment– Signed 2’s compliment

• Signed 2’s compliment are widely used for manipulation

• Signed number is used in mantissa in floating point representation

Addition and Subtraction with signed magnitude

Algorithm

• When the sign of A and B are identical(or different) add the two magnitude and attach the sign of A to the result

• When the sign of A ans B are different (identical), compare the magnitude and subtract the smaller compare the magnitude and subtract the smaller number from the larger. Choose the sign of result to be the sane as A if A > B or complement of sign A if A < B

• If two magnitudes are equal , subtract B from A and make the sign of result positive

• Q: perform above algorithm when

– A=+5 and B=+3

– A=-5 and B=+3

Hardware Implementaion

• The hardware of signed magnitude for addition and subtraction consist of two 8 bit registers A and B

• Register A (B) consist of 1 bit flip-flop As (Bs) which denote the sign of content of register A

• For positive value flag is set to 0 and for negative value flag is set to 1

• In diagram there is complimnenter below register B , and is used to compliment value of register B

• The mode control decides whether the value of B register be complemented or notcomplemented or not– For M=0, no compliment – For M=1, value of B is complimented and then only passed to adder

• The content of registers A and B are added in adder• One bit F/F E contains the carry of output• Finally, sum is loaded in register AWhy AVF(Add overflow)?• If the compliment is 1’s compliment, the value of AVF is added and

for 2’s compliment it is ignored

Hardware algorithm

• Two siigns As and Bs are compared using XOR – If o/p=0, same sign – If o/p=1 different sign

• For add operation– Identical sign means magnitude should be added

• Micro-operation EA= A+B, EA is a register that combine E and A

• Carry in E after the addition constitute an overflow if it is equal to 1 and thus E is transferred to AVFequal to 1 and thus E is transferred to AVF

– Different sign means subtraction of magnitude• A - 2’s compliment of B• No overflow, AVF cleared• If E=1 it means A>=B, and number in A is correct result• If E=0 it means A< B sign As must be complimented to avoid

negative zero and A must be 2’s complimented• Correct result will be in A register

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• Q: Mark each individual path in the flow chart by a number and then indicate the overall path that the algorithm takes when the following signed magnitude number are computed. In each case give the value of AVF. The leftmost bit in the following number represent the signed bitrepresent the signed bit

a) 0 101101 + 0 011111b) 1 011111 + 1 101101c) 0 101101 – 0 011111d) 0 101101 – 0 101101e) 1 011111 – 0 101101

Addition and subtraction of signed 2’s compliment data

• Already done in previous chapter

Sum is obtained by adding the contents of AC and BR including sign bits

Overflow f/f V is set to 1 if XOR of last Overflow f/f V is set to 1 if XOR of last two carries is 1 else cleared

Subtraction is carried out by adding the content of AC to the 2’s compliment of BR

In comparison to signed magnitude algorithm it is much simpler

Q: perform 33 + (-45) using this algorithm

Multiplication Algorithm

• A complex operation compared with additionand subtraction

• Many algorithms are used, esp. for largenumbers

• Simple algorithm is the same longmultiplication taught in grade schoolSimple algorithm is the same longmultiplication taught in grade school— Compute partial product for each digit— Add partial products

•

Hardware implementation

• Two more registers other than multiplier and multiplicand(B)• Multiplier stored in Q and its sign in Qs• SC is set to value equal to the number of bits in multiplier• The sum of A ans B forms partial product which is transferred to EA• Both partial product and multiplier are right shifted shr EAQ• SC is decremented by 1 after forming a partial product• SC is decremented by 1 after forming a partial product• When SC =0, product is formed and process stops• The LSB of A is shifted to MSB of Q• The bit from E is shifted to MSB of A and 0 is shifted into E• After the shift one bit of partial product is shifted into Q pushing

multiplier bits one position to the right• In this way the rightmost bit of q Designated by Qn will hold the

multiplier bit to be inspected next

Hardware algorithm

Signed 2’s compliment Multiplication

• Booth Algorithm is used– It operates on the fact that string of 0’s in multiplier need no

addition but just shifting– String of 1s in the multiplier from bit weight 2k to 2m can be

treated as 2k+1 – 2m

• For eg M*14(0001110)=M*23+1 – M*21• For eg M*14(0001110)=M*2 – M*2

– This algorithm also requires inspection of multiplier bits and shifting of partial product

– Prior to shifting multiplicand may be added to or subtracted from the partial product or left unchanged according to following rule• Subtracted if there is first least significant 1 in string of multiplier • Added if it encounters 0 provided that there was a previous 1 in string

o 0s in multiplier• Left unchanged when multiplier bit is identical to the previous bit

Hardware for booth algorithm

Array multiplier

• The discussed algorithm requires inspection of individual bits of multiplier and forming partial product--- which requires sequence of add and shift micro-operations

• Rather it can be done by single micr-operation • Rather it can be done by single micr-operation using combinational circuit that forms product bits all at once

• Fast way of multiplication

• However, array multiplier needs large no of gates and thus not economical

• Multiplication of individual bits are carried out by AND gates

• Partial product is formed by using half- adder

• Similarly higher configuration can be made• Similarly higher configuration can be made

• For j bit multiplier and k bit multiplicand we need j*k AND gate and (j-1)*k adders to produce j+k bits products