C4NP technology: Manufacturability, yields and reliability

C4NP Technology: Manufacturability, Yields and Reliability

Eric D. Perfecto, David Hawken, Hai P. Longworth, Harry Cox, Kamalesh Srivastava, Valerie Oberson**, Jayshree Shah, and John Garant

IBM Systems & Technology Group (STG) 2070 Route 52, Hopewell Junction, N.Y.12533

**IBM Canada, 23 Blvd de L'Aeroport, Bromont QC J2L 1A3 email: [email protected], phone: (845-894-4400),

Abstract:

As a part of IBM movement from Pb-rich solders to Pb-free solder, a new low cost process has been developed to deposit the solder to a capture, or under bump metal (UBM) pad, with Suss MicroTech Inc as the equipment partner. The controlled collapsed chip connection new process (C4NP) has moved, over the last 2 years, from development into manufacturing for 300 mm wafers. During this transition, a great number of process improvements have resulted in high fabrication yields. Manufacturing robustness has been achieved by clearly identifying the processes which affect the C4 structural integrity. The solder composition has been optimized to improve its mechanical properties as well as low alpha emission rate requirement.

Sector partitioning methodology was used to obtain root cause for various defects which then, through replication studies, were confirmed. Key process improvements in the capture pad build, mold fabrication, and mold fill tool have been accomplished as the process has matured. Thermal undercut was identified as a mechanism of Cu seed consumption when no top Cu was available on top of the Ni UBM.

C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Yield learning model shows a 15% defect reduction per month since the start of the C4NP program. Technology qualification for 300 mm wafers with 200um and 150 um pitch Pb-free C4 bumps has been successfully completed.

Introduction:

C4NP is currently being used at IBM for all 300mm lead-free wafer bumping for flip chip interconnect. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass mold. The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/soft contact, and solder bumps are transferred onto the entire wafer in a single process step without the complexities associated with liquid flux [1, 2].

Over the last 2 years, the C4NP technology has moved from development to manufacturing with the first Pb-free production base on C4NP delivered on July, 2007. In order to achieve this short development cycle, IBM partnered with Suss MicroTech Inc. for the commercialization of the tools which enabled this new technology. The first prototype tools were low volume development tools with some operator intervention. The current mold fill and inspection tools are fully automatic designed for 150 wafers per day. As the fill

and transfer technologies progressed, the improvements are adopted into the high volume manufacturing (HVM) tools.

Initial implementation of the C4NP was on 200 um C4 pitch products [3]. Extension of this technology to 150 um pitch will be discussed in this paper, and 50 um pitch using C4NP has been reported elsewhere [4]. In addition to tighter C4 pitch, C4NP has the ability to accommodate various solder types with a simple fill head change. As the semiconductor speed improvements move this technology to the use of low k materials, chip package interactions (CPI) become more pronounced necessitating the use of softer solders, which may require small amount of additives for improved mechanical properties [5, 6]. In addition, Pb solders can be also transferred using the same tooling with very small modification [7].

Through the use of lean manufacturing practices the C4NP yield has improved significantly. Root cause analysis has resulted in process and robustness improvements in the capture pad, as well as in the mold fabrication, and mold fill areas. A yield learning model was applied to C4NP process. Finally, C4NP qualification results for the 150um pitch will be presented. C4NP Program Description and applications

Wafer Level Packaging (WLP) utilizes solder sphere placement technology to manufacture the bumps. C4NP is an alternate technology which has proven to be suitable for a broad range of solder bump pitches. At IBM, C4NP has focused manufacturing in 200um and lower pitches for Pb-free solder bumps whereas electroplating technique is currently used for high lead bumps [8]. Pb-free solder is stiffer and has lower melting point compared to high lead solder. Pb-free solder reacts quickly with UBM. Pb-free C4s are more prone to fatigue than leaded C4. Proper material selections become key criteria for Pb-free bumping to ensure C4 integrity, corrosion and electromigration.

For 130nm and coarser chip wiring applications, C4 bumps are placed on 200um or higher pitch. In advanced nano-technology in 45nm and 32nm nodes, the C4 bump pitches are reduced to 150um. Typical C4 bump dimensions for 200 um and 150 um pitch are listed in Table 1.

C4 Pitch C4 Diameter (um) UBM Diameter (um)

200um 125 110

150um 100 85

Table 1: Typical C4 bump dimensions

978-1-4244-2231-9/08/$25.00 ©2008 IEEE 1641 2008 Electronic Components and Technology Conference

For the highest C4 joint performance, bump UBM diameter and solder mask opening dimensions are matched. The laminate FCA pad coplanarity is achieved by coining solder volume screened in resist mask opening. For fine pitch C4 bump, coplanarity is tighter to eliminate solder non wets during chip assembly process. Top level wiring needs limit the size of the laminate FCA pad diameter, thereby limiting the entire C4 joint density.

Solder Material Options

Choice of Sn-Ag solder composition for device joining purposes is dependent on the design factors including, liquidus temperature being relatively low (about 220 C), elimination of formation of rod-like Ag3Sn precipitate, reduction in suppression of solidus, relatively low hardness, and longer life expectation from the point of electro-migration behavior. Ag-Sn phase diagram using thermodynamic equilibrium concept, shows that Ag3Sn should form in any alloy with silver content more than 0 wt%. However, because of kinetics (of solidification) considerations Ag3Sn precipitation can be suppressed in dilute Sn-Ag alloys.

The precipitation of rod-like Ag3Sn phase during chip-joining process has been observed in alloy containing as low as 2.3%Ag. Because of the need for suppression of rod-like Ag3Sn precipitates and reduction in hardness, silver content is further reduced. Therefore Sn-<2%Ag alloys together with Sn-0.7%Cu have been examined for suppression of solidus, micro-hardness of the module level joint using laminates with Sn-0.7%Cu and Sn-3.5%Ag-0/7%Cu solder pastes. Solder composition effects on undercooling has been reported earlier for a BGA solder earlier [9]. Microhardness of solder joint are sensitive to the percent of Ag content (see Figure 2). This result agrees with the improvements on stress relaxation and white bump reduction observed with reduced Ag content [10].

C4 Bumps were also examined by X-ray radiographic technique for hundreds of wafers and found to be completely void-free. Alpha emission rate of the solder is kept at a low level from the point of minimization of soft error (SER) incidence. In our solder design, alpha-emission–rate is kept below 0.005 counts per cm^2 per hour. This is achieved by the vendor-confidential refining process (Senju Comteck Inc.). Also, we have found that the alpha emission rate of the as received solder sample plates does not increase with time

for measurements completed up to 180 days, unlike low-alpha emission type of leaded solder.

Sn-Ag and Sn-Cu were evaluated in detail for assembly performance optimization. It may be noted that a softer solder is desirable, since it allows accommodating part of the strain caused by the mismatch of thermal expansion between silicon and organic laminate. However, Sn-Ag alloys in spite of being relatively harder than Sn-Cu, are preferred because of superior electromigration performance [11]. Reduced Ag composition was found optimum for the bump solder. Capture Pad Process Optimization

A capture pad structure is required to accept the solder during the transfer process. It is comprised of four layers. Each of the layers serves a specific function to guarantee the performance and reliability of the final product [3]. The Capture Pad process flow is depicted in Figure 3. The diameter of the TiW and Cu seed layers are integral to the reliability of the structure and need to be rigorously controlled.

The photolithography process and subsequent electroplating operations generate tight UBM diameter tolerances. Final capture pad diameters are defined by the seed layer etches. The Cu seed layer is removed using an ammonium persulfate solution. During the etch process, the top electroplated Cu film is exposed to the etchant. The electroplated Cu is intentionally plated thicker to accommodate some loss during the seed layer removal. The chemical undercut observed during Cu seed etch is very low; typically less than 1 um per side. The resultant Cu seed diameter then defines the TiW etch. A hydrogen peroxide based chemistry is used to remove the TiW. Again, the typical undercuts observed during this process is less than 1 um/side. The resultant capture pad is shown in Figure 4. After final surface clean processes, the structure is ready for the solder transfer process

Control of the consumption of the electroplated copper during the seed Cu etch is also an important aspect of the capture pad build process and product reliability. At transfer,

Module Level Microhardness Trend with Increasing Ag Content

Ag% Content in Sn

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Module Level Microhardness Trend with Increasing Ag Content

Ag% Content in Sn

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Figure 2: Module level solder joint micro-hardness

Figure 1: Typical module joint X-section and vickers hardness measurement indentation

1642 2008 Electronic Components and Technology Conference

Reflow Alloys Consumed Ni(µm)

Cu Thermal undercut

(µm)T0 (chip) SnAg 0.3 3.9T0 (chip) SnCu 0.3 3.3

Chip/LaminateT14 SnAg/SAC 0.5 3.7T14 Sn-Ag/SnCu 0.4 2.6T14 Sn-Cu/SAC 0.4 3.5

Table 2: Evaluation of various solders after 14 reflows on UBM undercut and Ni consumption

both the electroplated Cu and the remaining seed Cu react with Sn to form CuSn intermetallics. The molten solder wets around the plated Ni and can aggressively reacts with the seed Cu film. Maintaining a minimum electroplated Cu thickness ensures minimal Cu seed perimeter reaction, which will be referred to as thermal consumption of the Cu seed or thermal undercut (see Figure 4). Typical Cu seed thermal undercuts are less than 4 um/side when electroplated Cu is present. Failure to maintain the minimum plated Cu film thickness can result in seed thermal undercuts of 10 um/side and greater. This excessive thermal consumption is undesirable since the Cu intermetallic has little adhesion to the TiW film.

Undercut on Bond & Assembly: To determine the thermal impact of the optimized chip join reflow profile (discussed later) on Cu undercut and Ni consumption selected Pb free C4 solder alloys (Sn-Ag and Sn-Cu) were assembled on SAC and Sn-Cu organic substrates.

Bare die (T0) and assembled modules as after 14 chip join reflows (T14) were x-sectioned and observed. Table 2 shows the Ni consumption and Cu seed thermal undercut, for both, as joined and after 14 reflows. No significant difference in Cu undercut was found on the various combinations.

Small, 0.1 to 0.2 µm, Ni consumption (UBM) was observed between the incoming devices and the assembled modules after 14 reflows. The electroplated Cu, when reacted with Sn, protects the Ni from the Sn [12]. Figure 5 shows typical x-section measurements after 14X reflows. Ni layer is uniform and within specifications. Cu undercut is within specifications.

Capture Pad Post Cu & TiW Etch

Electroplated Cu

Electroplated Ni: ~ 2.0um

Sputtered Cu, Sputtered TiWPolyimide Surface

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Undercut < 1um

Capture Pad Post Cu & TiW Etch

Electroplated Cu


Sputtered Cu, Sputtered TiWPolyimide Surface

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Capture Pad / Solder Post Transfer

(Cu,Ni)Sn Intermetallic


Polyimide Surface

Bulk SnAg SolderBulk SnAg Solder

Thermal Undercut

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Capture Pad / Solder Post Transfer

(Cu,Ni)Sn Intermetallic


Polyimide Surface

Bulk SnAg SolderBulk SnAg Solder

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Sputtered Cu, Sputtered TiW

Figure 4: Schematic diagram of the capture pad before and after solder transfer

Cu layer

Ni layer

Cu layerCu layer

Ni layerNi layer

Figure 5: Assembled modules after T14 reflows over a TiW/Cu/Ni UBM. The 3.7 um Cu seed consumption is due to thermal undercut. Ni layer is uniform after 14X reflows (few mouse bits).

TiW and Cu Seed Sputter

Resist Apply

Expose & Develop

Resist Strip

Cu Etch

TiW Etch

Ni and Cu Plate

C4NP Solder Transfer

Figure 3: Capture pad process


Figure 7: Pictorial X-section of solder in cavity post mold fill with different environments

Mold fill Improvements Over the past two years, the C4NP Mold fill process has

evolved to become a state of the art manufacturing process. Key changes in the overall process and tool set has set the stage. Key changes include:

1. Vacuum Head Design – To increase throughput and fill yields 2. Automated tool: To increase Throughput and combine the learning on the JDA Beta tool set. 3. Environmental controls: To control the solder outputs 4. Process flexibility to accommodate various C4 pitches

Vacuum Head Design: Key changes were made in the head design which resulted in many process and throughput improvements. First, a seal cross section change was made to keep the seal from rolling during solder fill. If the seal rolls, solder would leak and spill out of the head. A “Loft” design was developed to prevent the seal from rolling. Second, the vacuum head was designed to evacuate the cavities of air and allow solder to freely fill the cavities. This allowed a 5x increase of fill speed over the previous process. It also eliminated the need to condition the seal for air escape. Third, the overall head was designed to allow for expansion as the head is heated. This is needed to keep the sealing surface flat during the fill. Forth, pre and post fill environments were installed on the head to control the environment on the leading and trailing head of the mold fill. This reduced the amount of oxides being generated during the fill and improved the overall process yields and seal life. Finally, unique solder ingot shapes were designed to control the solder compositions at fill.

Fill Environment: The post fill environment has the most effect on the cavities shapes. When molds are filled with a pure N2 environment, there is no oxide generated on the solder, and the solder tends to go to a natural spherical shape. Additionally, the mold surface is also playing a roll in the final shape of the cavity. Figure 7 illustrates the solder shape when filled under various environments.

Seventeen different solder Alloys were evaluated over the past year. The effect of the alloying elements and resulting super cooling affects were the most dominant feature during the fills. SnCu and SnAg solders are filled using the same process. Fill parameters were slightly modified to successfully fill solders with additives, such as Ni, Zn, and Co.

C4 Product Pitch: Successful demonstrations have been done in filling a variety of mold with various C4 pitches. They have ranged from 50um to 250 um. It was found that changes in the environment were necessary as the pitch varied. In order to fill 25 um cavities, the fill atmosphere had to be pure nitrogen to prevent the solder from bridging between C4 cavities. With higher pitch molds, oxygen containing environment was required which kept the solder flat within the cavities. This facilitated the mold inspection. Yield Improvements

A significant yield improvement has occurred as the process matures and the manufacturing tools were installed. The yield data is based on RVSI inspection. Figure 8 shows the pareto chart for various months over a two year period. As Figure 8 shows, contamination has been and continues to be the number one yield detractor. Initially, the main source of contamination was attributed to residual resist which resulted from the stripping process. A new resist stripper was implemented eliminating this defect type. Additionally, the low volume manufacturing tools were placed in a segregated area with improved cleanliness. These tools required manual handling of the wafers and molds. But as manufacturing moved to HVM tools with FOUP to FOUP automatic handling, this source of contamination was eliminated.

Another source of contamination occurred at the capture pad definition. Here laminated negative resist is used to define the UBM, and contaminants were landing on top of the resist resulting in deformed C4s and bridges or shorts. This defects source was also eliminated through process and tool optimizations. Finally, mold yield improvements resulted in a significant reduction of missing C4s and volume and/or co-planarity losses [13].

Figure 6: Mold fill head


C4NP RVSI Inspection: Yield Learning ModelCalculated Learning: R= 15% Defect reduction per month

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C4NP RVSI Inspection: Yield Learning ModelCalculated Learning: R= 15% Defect reduction per month

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Figure 9: Actual yield and projection for 2007 based on 2006 learning

All this learning was modeled using a yield learning model which was previously applied to IBM multilevel – thin film fabrication [14]. It assumes that yield detractors (small & large) appear completely random within a wafer as well as from wafer to wafer, and are statistically independent. The yield learning can be represented as a constant reduction of defects or yield detractors. Yt = exp {-L (1-R) t } (1) where L = initial number of defects per part. R = rate of defect reduction of L per period t = time period. A linear expression results by taking the double logs: ln{-ln(Yt)} = ln(L) + t ln(1-R) (2) From expression (2), L & R can be estimated from the historical yield data. This yield model was applied to the 2006 data and then projected and compared to the actual 2007 data. Figure 9 shows both, the actual data and the model data which had an R-square of 0.88. The model showed a monthly defect

reduction rate, R, of 15% over the 2 year period. Since development and manufacturing occurred in the same line, there was no change in the defect reduction rate as production started. Assembly optimization

Pb free solder alloys have higher yield stress, higher creep resistance than Pb-rich solder alloys. Pb-free C4 interconnect stress build up during Chip Join cooling (reflow), due to CTE mismatch between device/organic carrier, can exceed device BEOL (Low K CVD) structure strength for specific design structure causing delamination / cracking. Thorough identification and characterization of the chip join process parameters impacting the stress build up are reported by Sylvestre, et al. [10].

Optimization of the chip join reflow profile to mitigate the cracking in the device BEOL structure resulted in a slower cooling rate, and a larger dwell above 217C. As Table 3 shows, flux material and cleaning process were modified for 150 um pitch C4 products.

March-06 July-06 Nov.- 06 March-07 July-07 Nov-07March-06 July-06 Nov.- 06 March-07 July-07 Nov-07

Mar-06 Jul-06 Nov-06 Mar-07 Jul-07 Nov-07 Contamination 48.77 42.08 55.56 61.73 66.77 60.91 Volume 17.18 21.78 22.22 19.40 21.36 18.85 Co-planarity 27.61 20.79 12.04 7.58 9.50 11.30 Bridges 5.21 3.96 5.56 9.17 1.78 1.21 Missing 1.23 11.39 4.63 2.12 0.59 7.73 Total 100 100 100 100 100 100

Figure 8: Pareto diagram of C4NP defects over time


Reliability Evaluation Test vehicle: The test vehicles for C4NP technology developments were specifically designed to evaluate all aspects of C4 reliability: joint integrity, solder fatigue, metal migration, temperature aging stability, tin whiskers, tin pest and electromigration. With the introduction of low-k CVD chip technology and tighter ground rules, chip package interaction (CPI) has become an increasingly important reliability issue. To evaluate CPI, the test vehicle was designed with full stacks of metal and dielectric layers comparable to actual products. Multiple via chains and serpentine structures were designed in several metal layers. To evaluate the C4’s, there are multiple 4-point test structures in the chip corners as well as under the center of the die. There are also stitched C4 patterns along the edges of the die and under the center of the die. Very precise continuity measurements of C4’s and leakage measurements between C4’s can be obtained.

There are four electromigration (EM) test sites. The EM test structures allow four-point probe measurements of C4 resistance of the stressed C4s along with a built-in thermal sensor and a short monitor. In addition, the 3 on 6 test vehicle allows EM testing on a stitched chain of C4’s. The 3 on 6 test vehicle description is shown in Table 4. Multiple processing

lots of actual product form factor hardware were also stressed along with the test vehicle lots for reliability verification and to assess process control and product quality.

C4 Integrity Evaluation: X-ray inspection performed post solder transfer in multiple locations, minimum of 450 C4 bumps, confirmed the absence of solder voids on C4NP wafers. The C4 bumps were RVSI inspected, and measured for coplanarity and solder volume. The integrity of C4 joints and underfill were evaluated on multiple processing lots of both test vehicle and product form factor hardware. Figure 10 shows the x-section of C4 after bond and assembly processing.

After chip joining to laminate and post JEDEC reflows, chips were pulled to determine tensile pull strength. The pulled chips along with the substrates were then inspected for voids, non-wets, fracture mode, delamination and any other anomalies. Underfill integrity is an essential part of module reliability in packaging applications with high chip/substrate CTE mismatch and/or non-hermetic condition. Module sonoscan, post BAT, is a standard operation since significant degradation in C4 fatigue life could occur in areas of poor adhesive bonding or underfill voids.

Reliability Stressing: Reliability evaluations encompassed standard JEDEC stress conditions (T/C, T/H/B, HAST, HTS, LTS) and several new stress conditions, designed specifically to evaluate lead free solders such as electromigration, tin whiskers and tin pest. Prior to stressing, all 4 on 8 test modules were subjected to JEDEC pre-conditioning (Level-3). Results for 4-on-8 C4s were previously reported [3]. Table 5 shows reliability stress results for 3-on-6 C4s test modules. Summary Through lean manufacturing principles, the C4NP has moved from development to a robust manufacturing process. Improvements at UBM definition, mold fabrication, and mold fill have resulted in a robust C4 structure. A consistent 15% monthly defect reduction, as calculated by the yield learning model, has been achieved.

Chip 3 on 6 Test Vehicle Chip Technology Low K CVD/BEOL Diced Chip Size (mm) 15.6 x 11.2 UBMMetal/ Pad Dia (um) TiW/Cu/Ni/Cu /85 No. of C4s 4985 C4s/Chip C4 Pitch (um) 150 C4 Solder Sn-Cu, Sn-Ag Package Laminate Design 3-2-3

Material & Buildup 679FG Core, GX-13 Size (mm) 42.5 x 42.5 TSM I/O Pads Dia (um) 80 um Module Assembly Lid 2 mm thick (one piece ) BSM Sn3.0Ag0.5Cu BGAs on

Cu OSP TV Chip /Module Process JEDEC Pre-Conditioning Special

30C/70%RH/120 Hrs Pre-Conditioning Temp. C 245 C / 3 X

Table 4: Test vehicle description

Test Conditions Duration Results DTC -55/125C 1250 cyc Pass DTC -40/125C 1250 cyc Pass ATC 0/100C 1500 cyc Pass

HAST 130C/85%RH 96 Hrs Pass THB 85C/85%/3.6V 1000 hrs Pass HTS 150C 1000 hrs Pass

C4 EM

110C/130C/150C-

0.5A/0.7A 2000hrs

Data supports up to 275watts

(assume 2.5V) at 100C, 100KPOH

WettabilityInitial Join Wettability ----

Good pull strength,no nonwetts

Table 5: Reliability data for 3 on 6

BA (Chip join) Operations 4on8 3on6Flux A A/B

Reflow A BCleaning A A/B

Table 3: 4on8 vs. 3on6 BA (Chip Joining) differences


C4NP is currently in manufacturing for all 200 um C4 pitch Pb-free products, and has passed the reliability on the 150 um C4 pitch test vehicle. Several process and materials improvements have been implemented for EM and chip package interaction robustness, including a lower %Ag solder, and bond and assembly optimization. The current structure supports up to 275watts at 100C, 100KPOH. Acknowledgments

The authors would like to acknowledge their management team for their support. Additionally, special thanks are due to Sung Kang and Sun K. Seo for the hardness measurements, Michael Gordon for the alpha measurement, all from Watson Research; Robert Alley for solder ICP from East Fishkill, and the FA team: Luc Patry from IBM Bromont, and Hsichang Liu and Charles Goldsmith, both from East Fishkill.

References 1. P. Gruber et al., “Low Cost Wafer Bumping”, IBM J.

Res. & Dev. Vol. 49 No. 4/5, July/September 2005. 2. E. Laine, K. Ruhmer, E. Perfecto, H. Longworth, D.

Hawken, “C4NP as a high-volume manufacturing method for fine-pitch and lead-free Flip Chip Solder Bumping” Proceedings of ESTC, IEEE, Dresden, Germany, September, 2006

3. A. Giri, E. Perfecto, et al., “Development and Implementation of C4NP Technology for 300 mm wafers,” Proceedings of 57th ECTC, Reno, June, 2007

4. Dang, D-Y Shih, et al., “50µm Pitch Pb-Free Microbumps by C4NP Technology,” Proceedings of 58th ECTC, Orlando, May, 2008

5. K.Moon, W. Boettinger, U. Kattner, F. Biancaniello, C. Handwerker, “Experimental and Thermodynamic Assessment of Sn-Ag-Cu solder alloys” J. Electron. Materials, .29(2000), p. 1122-1236

6. T. Siewert, S. Liu, D. Smith, J.C. Madeni, “Data Base for solder Properties with Emphasis on Lead-Free Solders”, Release 4.0 , National Inst.of Standards & Technology, Colorado School of Mines, Publication, Feb 2002

7. E. Perfecto. et al., “C4NP Technology: Present and Future,” Extended Abstract of IMAPS Device Packaging Conference, 2008

8. J. Shah, D. Hawken, H. Longworth et al. “C4NP Lead free versus Electroplated High Lead Bumps” Proceedings of IPC Works 2006, Dallas, September, 2006.

9. I. de Sousa, D. Henderson, L. Patry, et al., “The Influence of Low Level Doping in Thermal Evolution of SAC Alloys Solder Joins with Cu pad Structures,” Proceedings of 56th ECTC, San Diego, May, 2006

10. J. Sylvestre, et al., “The Impact of Process Parameters on the Fracture of Brittle Structures During Chip Joining on Organic Laminates,” Proceedings of 58th ECTC, Orlando, May, 2008

11. M. Lu, D-Y Shih, et al., “Comparison of Electromigration Performance for Pb-free Solders and Surface Finishes,” Proceedings of 58th ECTC, Orlando, May, 2008

12. C. Jurenka, J. Kim, M. Wolf, et al., “Effect of Cu Thickness on the Stability of a Ni/Cu Bilayer UBM of lead free Microbumps During Liquid and Solid State Aging”, Proceedings of 55th ECTC, Orland, June, 2005

13. E. Laine, E. Perfecto, B. Campbell, J. Wood, J. Busby, J. Garant, L. Guerin “C4NP Technology for Lead Free Solder Bumping” , Proceedings of 57th ECTC, Reno NV, May, 2007.

14. E. D. Perfecto, K. Saji, K. Desai & J. Saltarelli, “IBM MCM-D/C Yield Learning Experience,” Microcircuits and Electronic Packaging, V 20, No. 4, Fourth Quarter, pp. 563-570 (1997)

Figure 10: Module X-section for 150 um pitch


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C4NP technology: Manufacturability, yields and reliability