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ECE2030 Introduction to Computer Engineering
Lecture 11: Building Blocks for Combinational Logic (2) Decoders/Encoders, Comparators
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech
2
1-to-2-Line Decoder
ADAD
1
0
AA D1D1 D0D00 0 11 1 0D0
D1A
3
N-to-M-Line Decoder (2N M)
A1 A0 D3 D2 D1 D00 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoderA0
A1
4
2-to-4-Line DecoderA1 A0 D3 D2 D1 D00 0 0 0 0 10 1 0 0 1 0
1 0 0 1 0 01 1 1 0 0 0
013
012
011
010
AADAAD
AAD
AAD
How about if no one should be enabled ?
A1A0 D0
D1
D2
D3
5
2-to-4-Line Decoder w/ EnableEn
A1
A0
D3
D2
D1
D0
0 X X 0 0 0 01 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0
013
012
011
010
AEnADAEnAD
AAEnD
AAEnD
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoderA0
A1
En
6
2-to-4-Line Decoder w/ EnableEn
A1
A0
D3
D2
D1
D0
0 X X 0 0 0 01 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0
013
012
011
010
AEnADAEnAD
AAEnD
AAEnD
A1A0 D0
D1
D2
D3
En
7
3-to-8-Line Decoder
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0
Truth Table
8
3-to-8-Line Decoder
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0
Truth Table
9
3-to-8-Line Decoder
A2 A1 A0 D7 D6 D5
D4 D3 D2 D1
D0
0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoder
A0
A1
En
D0
D1
D2
D3
D0
D1
D2
D3
2-to-42-to-4-line-line
decoderdecoder
A0
A1
En
D4
D5
D6
D7
A0
A1
A2
10
Implementing Logic w/ Decoder
D0
D1
D2
D3
3-to-83-to-8-line-line
decoderdecoderA0
A1
A2D4
D5
D6
D7
5,7)M(0,1,2,3,Z)Y,F2(X,
m(1,2,6,7)Z)Y,F1(X,
XX
YY
ZZF1F1
F2F2
11
BCD-to-7-SegmentDecoder
BCD-to-7-Segment Decoder• Another kind of decoder
a b c d e f g
aa bb cc dd ee ff gg
AA
BB
CC
DD
12
BCD-to-7-SegmentDecoder
BCD-to-7-Segment Decoder• Another kind of decoder
a b c d e f g
aa bb cc dd ee ff gg
AA
BB
CC
DD
ab
c
d
eg
f
13
BCD-to-7-SegmentDecoder
BCD-to-7-Segment Decoder• Decode “2” and
show
a b c d e f g
aa bb cc dd ee ff gg
AA
BB
CC
DD
ab
c
d
eg
f0
0
1
0
11011
10
14
BCD-to-7-SegmentDecoder
BCD-to-7-Segment Decoder• Decode “4” and
show
a b c d e f g
aa bb cc dd ee ff gg
AA
BB
CC
DD
ab
c
d
eg
f0
1
0
0
01100
11
15
BCD-to-7-Seg. Decoder Truth TableA B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 01 0 0 0 1 0 1 1 0 0 0 02 0 0 1 0 1 1 0 1 1 0 13 0 0 1 1 1 1 1 1 0 0 14 0 1 0 0 0 1 1 0 0 1 15 0 1 0 1 1 0 1 1 0 1 16 0 1 1 0 0 0 1 1 1 1 17 0 1 1 1 1 1 1 0 0 0 08 1 0 0 0 1 1 1 1 1 1 19 1 0 0 1 1 1 1 0 0 1 1
>10
All other inputs 0 0 0 0 0 0 0
16
Design Each Output Individually “a”
A B C D a0 0 0 0 0 11 0 0 0 1 02 0 0 1 0 13 0 0 1 1 14 0 1 0 0 05 0 1 0 1 16 0 1 1 0 07 0 1 1 1 18 1 0 0 0 19 1 0 0 1 1
>10
All other inputs 0
00 01 11 10
00 1 0 1 1
01 0 1 1 0
11 0 0 0 0
10 1 1 0 0
ABCD
CBABDACDADBAa
17
Design Each Output Individually “b”
A B C D b0 0 0 0 0 11 0 0 0 1 12 0 0 1 0 13 0 0 1 1 14 0 1 0 0 15 0 1 0 1 06 0 1 1 0 07 0 1 1 1 18 1 0 0 0 19 1 0 0 1 1
>10
All other inputs 0
00 01 11 10
00 1 1 1 1
01 1 0 1 0
11 0 0 0 0
10 1 1 0 0
ABCD
CDADCABACBb
18
M-to-N-Line Encoder (M2N)
D0
D1
D2
D3
2-to-42-to-4-line-line
DecoderDecoderA0
A1
En
D0
D1
D2
D3
4-to-24-to-2-line-line
EncoderEncoderA0
A1
Ac
19
4-to-2 Encoder
D3 D2 D1 D0 A1 A00 0 0 1 0 00 0 1 0 0 10 1 0 0 1 01 0 0 0 1 1
Since Dx=1 only in one column at a time A0 = D1 + D3A1 = D2 + D3
00 01 11 10
00 X 0 X 1
01 0 X X X
11 X X X X
10 1 X X X
D3 D2D1 D0
D0D2or D3D1A0
For A0
00 01 11 10
00 X 0 X 0
01 1 X X X
11 X X X X
10 1 X X X
D3 D2D1 D0
D0D1or D3D2A1
For A1
20
8-to-3 EncoderD7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A00 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1
Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7
21
Example 1 of an Encoder
Only point to one single reading at a time.
22
Example 2 of an Encoder
D0
D1
D2
D3
8-to-38-to-3-line-line
EncoderEncoder
A0
A1
A2D4
D5
D6
D7
Amy
Brian
Cathy
Dave
Ellen
Frank
Gina
Hugh
Ac
0
0
0
0Activeor not
1
1
0
1
?
?
?
1
23
8-to-3 Priority EncoderD7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 XX 0 0 1 1
0 0 0 0 0 1 XX XX 0 1 0 1
0 0 0 0 1 XX XX XX 0 1 1 1
0 0 0 1 XX XX XX XX 1 0 0 1
0 0 1 XX XX XX XX XX 1 0 1 1
0 1 XX XX XX XX XX XX 1 1 0 1
1 XX XX XX XX XX XX XX 1 1 1 1
24
4-to-2 Priority Encoder
D3 D2 D1 D0 A1 A0 Active
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 XX 0 1 1
0 1 XX XX 1 0 1
1 XX XX XX 1 1 1
00 01 11 10
00 0 0 0 0
01 1 1 1 1
11 1 1 1 1
10 1 1 1 1
D3 D2D1 D0
D3D2A1
For A1
Or using simplification property
D2D3D2D3D3A1
25
4-to-2 Priority Encoder
D3 D2 D1 D0 A1 A0 Active
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 XX 0 1 1
0 1 XX XX 1 0 1
1 XX XX XX 1 1 1
00 01 11 10
00 0 0 1 1
01 0 0 0 0
11 1 1 1 1
10 1 1 1 1
D3 D2D1 D0
D1D2D3A0
For A0
Or using simplification property
D1D2D3D1D2D3D3A0
26
4-to-2 Priority Encoder
D3 D2 D1 D0 A1 A0 Active
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 XX 0 1 1
0 1 XX XX 1 0 1
1 XX XX XX 1 1 1
00 01 11 10
00 0 1 1 1
01 1 1 1 1
11 1 1 1 1
10 1 1 1 1
D3 D2D1 D0
D0D1D2D3Active
For Active
27
4-to-2 Priority Encoder Schematic
D3D2A1
D1D2D3A0
D0D1D2D3Active
D3
D2
D1
D0
A1
A0
Active
28
8-to-3 Priority Encoder (A2)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 10 0 0 0 0 0 1 XX 0 0 1 10 0 0 0 0 1 XX XX 0 1 0 10 0 0 0 1 XX XX XX 0 1 1 10 0 0 1 XX XX XX XX 1 0 0 10 0 1 XX XX XX XX XX 1 0 1 10 1 XX XX XX XX XX XX 1 1 0 11 XX XX XX XX XX XX XX 1 1 1 1
D7D6D5D4D7D6D5D4D5
D7D6D5D6D4D5D6
D7D6D7D5D6D7D4D5D6D7A2
29
8-to-3 Priority Encoder (A1)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 10 0 0 0 0 0 1 XX 0 0 1 10 0 0 0 0 1 XX XX 0 1 0 10 0 0 0 1 XX XX XX 0 1 1 10 0 0 1 XX XX XX XX 1 0 0 10 0 1 XX XX XX XX XX 1 0 1 10 1 XX XX XX XX XX XX 1 1 0 11 XX XX XX XX XX XX XX 1 1 1 1
D7D6D3D4D5D2D4D5
D7 D6D3)D2D3(D4D5
D7D6D3D4D5D2D3D4D5
D7D6D3D4D5D6D2D3D4D5D6
D7D6D7D3D4D5D6D7D2D3D4D5D6D7A1
30
8-to-3 Priority Encoder (A0)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 10 0 0 0 0 0 1 XX 0 0 1 10 0 0 0 0 1 XX XX 0 1 0 10 0 0 0 1 XX XX XX 0 1 1 10 0 0 1 XX XX XX XX 1 0 0 10 0 1 XX XX XX XX XX 1 0 1 10 1 XX XX XX XX XX XX 1 1 0 11 XX XX XX XX XX XX XX 1 1 1 1
D7D5D6D3D4D6D1D2D4D6
D7D5)D3)D1D2(D4(D6D7D5)D3)D1D2D3(D4(D6
D7D5)D3D4D1D2D3D4(D6 D7D5)D3D4D5D1D2D3D4D5(D6
D7D5D6D3D4D5D6D1D2D3D4D5D6
D7D5D6D7D3D4D5D6D7D1D2D3D4D5D6D7A0
31
8-to-3 Priority Encoder (All)D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 Activ
e0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 10 0 0 0 0 0 1 XX 0 0 1 10 0 0 0 0 1 XX XX 0 1 0 10 0 0 0 1 XX XX XX 0 1 1 10 0 0 1 XX XX XX XX 1 0 0 10 0 1 XX XX XX XX XX 1 0 1 10 1 XX XX XX XX XX XX 1 1 0 11 XX XX XX XX XX XX XX 1 1 1 1
D7D6D5D4D3D2D1ActiveD7D5D6D3D4D6D1D2D4D6A0
D7D6D3D4D5D2D4D5A1
D7D6D5D4A2
32
1-bit Magnitude ComparatorA B A?B
0 0 A=B
0 1 A<B
1 0 A>B
1 1 A=B
A BA > BA = BA < B
BA BA
BA BA
BA BA
Single bit comparison
33
2-bit Magnitude Comparator (unsigned)
)BA)(BA( B)(A
BA)BA(BA B)(A
B)ABA(BA B)(A
0011
001111
001111
A BA > BA = BA < B
Two-bit comparison
2 2
A1A0B1B0
34
2-bit Magnitude Comparator (unsigned)
A BA > BA = BA < B
Two-bit comparison
2 2
A1A0B1B0
01
00111
00111
nnn
XX B)(ABAXBA B)(A
BAXBA B)(A
BA XAssign
35
3-bit Magnitude Comparator (unsigned)
Three-bit comparison
A2A1A0B2B1B0
012
001211222
001211222
nnn
XXX B)(ABAXXBAXBA B)(A
BAXXBAXBA B)(A
BA XAssign
A BA > BA = BA < B
3 3
36
4-bit Magnitude Comparator (unsigned)
0123
00123112322333
00123112322333
nnn
XXXX B)(ABAXXXBAXXBAXBA B)(A
BAXXXBAXXBAXBA B)(A
BA XAssign
Four-bit comparison
A3A2A1A0B3B2B1B0A B
A > BA = BA < B
4 4
37
4-bit Magnitude Comparator
0123
00123112322333
00123112322333
nnn
XXXX B)(ABAXXXBAXXBAXBA B)(A
BAXXXBAXXBAXBA B)(A
BA XAssign
B3 A3 A2 A1A0B2 B1B0
X3X2X1X0
A>B
A<B
A=B
38
Cascading Comparator
A BA > BA = BA < B
4 4
AGTBin
AGTBoutAEQBoutALTBout
Inputs fromPrior stage (Lower order bitsLower order bits)
AEQBinALTBin
ExtraComb.Logic
Outputs to Next stage (Higher order bitsHigher order bits)
AGTBoutAGTBout = = (A>B) + (A=B) · AGTBin(A>B) + (A=B) · AGTBinAEQBoutAEQBout = = (A=B) · AEQBin(A=B) · AEQBinALTBoutALTBout = = (A<B) + (A=B) · ALTBin(A<B) + (A=B) · ALTBin
39
16-bit Cascading Comparator
A BAGTBinAEQBinALTBin
4 4
AGTBoutAEQBoutALTBout
A[3:0] B[3:0]
A BAGTBinAEQBinALTBin
4 4
AGTBoutAEQBoutALTBout
A[7:4] B[7:4]
A BAGTBinAEQBinALTBin
4 4
AGTBoutAEQBoutALTBout
A[11:8] B[11:8]
A BAGTBinAEQBinALTBin
4 4
AGTBoutAEQBoutALTBout
A[15:12]B[15:12]
0
1
0
A>B
A<B
A=B
B[15:0]A[15:0]
