Lecture18

S. Reda EN160 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 18: Scaling Theory


Moore’s Law

Moore’s Law. The number of transistors in an integrated circuit doubles every 2 years. IBM Cell

234M transistors in die size of 221 mm2


Scaling of MOS transistors

minimum feature size(gate length)

1.2nm

Current oxide thickness ~ 1.0 – 2.0nm thickness 3 – 4 atomic layers of oxide

Power supply voltage scaling


Scaling

Avg transistor price is 0.1 μcent!

Fewer and fewer companies can afford to have their own foundries

Scaling of lithographic wavelength

Number of transistors shipped


Device scaling

(very idealistic NMOS transistor)

doping increased by a factor of S

scale

Increasing the channel doping density decreases the depletion width improves isolation between source and drain during OFF status permits distance between the source and drain regions to be scaled

(scaled down by L)


Implications of ideal device scaling


Historically frequency scaled by more than S

Intel VP Patrick Gelsinger (ISSCC 2001)“If scaling continues at present pace, by 2005, high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun.”


Scaling of standby (leakage) power

Even if Vt is kept constant after scaling, Poff scales up by S if tox is scaled down by S

Vt must be scaled down if VDD is scaled down (otherwise ISAT is weaker and transistor is slow)

Standby power would further increase by 10 for every 0.1V reduction of Vt

)(1 mkT

qV

oxoff

t

et

P

Standby power

bottleneck


Power/performance tradeoffs

Threshold voltage (Vt)

Po

we

r su

pply

vol

tag

e (

Vd

d)

increasingperformance

higher active power

higher leakage

[Taur, 01]


Interconnect scalingw

h

st

lw: width of interconnect (layer dependant)s: spacing between interconnects with same layerh: dielectric thickness (spacing between interconnects in two vertically adjacent layers)l: length of interconnectt: thickness of interconnect


Constant thickness scaling versus reduced thickness scaling

S

w

t

S

l

wt

S

l

S

tS

w

wt

l lreduced thickness scaling constant thickness scaling


Implications of ideal interconnect scaling


Interconnect delay is dominating gate delay

bottleneck

Repeaters can help but…


With scaling the reachable radius of a buffer decreases we need more and more buffers

A corner-to-corner (BL-UR) wire in Itanium (180nm) requires 6 repeaters to span die

Repeaters consume chip area; consume power; add vias

repeaters required to buffer Itanium global

interconnects

bottleneck


Summary

Done with chapter 4:

Delay estimationPower estimation Interconnects and wire engineeringDesign MarginsScaling theory

Business

Lecture18