May 9, 2016 1

ESL Virtual Platform for

Early Software Development

Ken Liao, Senior Associate VP, Faraday

May 9, 2016 2

• Faraday at a glance

• Purpose of virtual platform service

• Drawback of traditional design flow

• Targets of ESL SystemC model based

virtual platform

• Experience sharing

Outline

May 9, 2016 3

Faraday At A Glance

23 years of excellence • Established 1993, TWSE IPO 1999

• 2015 revenue : US$206M - 110M chips/year - Service 50% of WW Semi top 50

• Total >2,200 tapeout - Proven 340M-gate SoC design/MP

Technology strength • 920 employees, >75% R&D

• Broad portfolio - 450 patents, 3000 IPs - USB, PCIE, MIPI, VBO,… - High-speed SerDes - Node span 28nm & above

• Application-based platforms - Cortex-A/M series

UMC partnership • Spun off from UMC

• UMC: FTC’s largest shareholder

• FTC: UMC’s primary DCA

Business service • Major business: ASIC & IP

• Value-added services - Selective technology co-

development - Solution-based design support - Cross-region sales channeling

May 9, 2016 4

History of ASIC Design Service

Evaluation

platform

Software platform Software package

support

Hardware platform Integrated SoC design

database

Drivers

Toolchain

OS

Library

RTL sign-off ASIC service

SoC integration

CPU & HSIO(USB2/3, SATA, PCIE, DDR) & Serdes

Library/ Memory/ Analog/Mixed-Signal IPs

Traditional netlist-in ASIC service

1993 1999 2003 2007

Now

32-bit Data 14-bit Address

FA626 v5TE

D32K/I32K SD/SDIO

NAND

CTRL

DDR II

CTRL

External Memory Interface

LCD

CTRL

SRAM

CTRL

AHB

CTRL

AES/DES

DDR II

CTRL 8-ch DMA

CTRL

APB

Bridge Timer(3)

Interrupt

CTRL

PLL Clock

CTRL

GPIO SSP(2) BTUART

AHB@ 133MHz

AHB@66MHz

8/16-bit data

AHB

Bridge

APB@33MHz

ESL Virtual Platform

2016

TLM

memory memory Memory

UART

DMA

SPI

INTC

USB

VIO VIO

SPI flash

CPU

IP

May 9, 2016 5

Purpose of Virtual Platform Service

Software development

ASIC development without Virtual Platform

ASIC development with Virtual Platform

Arch design SoC hardware development

Arch design SoC hardware development

Gained time to market

Manufacturing Software development

• Early software development

• Identify architecture and hardware bugs

• Shift left the schedule

May 9, 2016 6

Result to schedule delay and limited SW development

Most efforts spend on debug HW instead of SW

development

Traditional HW-Based Prototyping

Problems and

More problems

DDR unstable

Peripheral IO

EVB bring up

CPU types

FPGA Timing

Design size

May 9, 2016 7

• Software development: Help bare-metal

software debug and application development

• Fast execution: ~100Mhz performance

• Hardware independent: Existing IP diagnostic

C code can run on virtual platform.

• Architecture optimization and thermal analysis:

Run application to extract bus traffic pattern

• CPU evaluation: Suitable for multi-core CPU

SoC, AMP and SMP

Where/How C-based Virtual

Platforms Help

May 9, 2016 8

Hybrid Prototyping

• Hybrid Prototyping: Virtual Platform + FPGA

• Faster Prototyping speed with HAPS FPGA

• Useful when IP model is not available

Virtual Platform on Host PC

PCIe Synopsys HAPS72

Reduce modeling effort

Cycle accurate functionality

High-speed real-world IO

UMR Bus

memory

TLM

memory memory

USB Transactor

Virtual Platform

CPU

UART

DMA

Transactor Customer’s

design

Synopsys HAPS72 FPGA

May 9, 2016 9

Virtual Platforms 3 Approaches…

Mo

de

l sp

ee

d

Fa

st

Slo

w

Modeling abstraction Detailed Abstract

FPGA EVB

• 20-40 MIPS

RTL simulation

• 1-2 KIPS

Hybrid • 20-100 MIPS

Virtual • ~100 MIPS

Co-Sim • 10-100 KIPS

May 9, 2016 10

• IP development effort

• Platforms

• Success story

Sharing our Experience

May 9, 2016 11

IP model

• FTC IP Models have same configuration as RTL code

• Complete IP model development flow for new IP

• 3 quality verification plans for each IP Model

IP Model Libraries

Unit test, Non-OS IP test, OS level test Model development flow

Faraday IP models - SDC021, SD card, MMC card

- UART010/VIO, TMR010 - SPI020, SPI NOR/NAND flash - DMAC020/DMAC030, INTC030 - OTG210 Device VIO/Host VIO - SMC030, I2C - LCD021, SSP010

Synopsys IP models • AHSATA, SATA Hard

Disk Drive • PCIE EP/RC • GMAC • HDMI RX/TX • USB 3.1, USB 2.0 • MIPI CSI2/DSI

Virtual Platform

TLM

DUT IP

CPU

UART

DMA

Specification

Documentation

Implementation

Verification

Release

Model under test

Test bench model with

inverse ports

ARM CPU fast Models • Cortex-A

− 64bit: A72, A57, A53 − 32bit: A17, A15, A9,

A8, A7, A5

• Cortex-R: R4, R5, R7 • Cortex-M: M3, M4 • Legacy: ARM7, ARM9,

ARM11

3.3 Kernel

Application(User)

Cortex

-A9

BSP

DMA

driver

SPI

Flash

driver

3D

driver

USB

Device

driver

USB

Host

driver

May 9, 2016 12

Virtual Platforms–Quickly Configurable

• GUI I/F can quickly re-build customized Virtual Platform

• Built A380-VP Virtual Platform for customer’s reference

• SW boot code & Linux driver is identical to A380 SoC

GUI interface

A380 SoC platform (SoCreative!IVＴＭ)

Starts software development Now

TLM

memory memory memory

UART

DMA

SPI

A380-VP

INTC

USB

VIO VIO

CPU

SDC

SPI flash SD card

Boot code development − Boot from UART I/F, SD card,

SPI flash, USB I/F

App/Driver development − Linux or other OS porting,

driver, middleware, app

May 9, 2016 13

AXI

memory memory Memory

USB Transactor

HAPS FPGA

LCDC

Encoder Decoder

• Customer’s problem

− New CPU and Middleware development

• Customer adopted a hybrid solution due to

− Right CPU & no CPU/ICE debugging effort

− Increase prototype capacity

− Complex IP model is not feasible

− Quick Linux bring up time (3s)

Hybrid Prototyping Success Case

Testchip SoC (CA9MP) Synopsys HAPS FPGA

Middle-ware development

TLM

memory memory memory

Virtual Platform

CA7MP

UART Transactor

AXI

FPGA

LCDC

CAP

May 9, 2016 14

RTL Co-simulation Case Study

• Customer A: Performance analysis

− Replace IP model with performance concerned IP

• Customer B: Power estimation

− RTL power pattern is too short

− Co-sim provides complete system patterns for

accurate result

RTL waveform

TLM

memory memory Memory

UART

DMA

SPI

Virtual Platform

INTC

USB

VIO VIO

SPI flash

CPU

IP

TLM

memory memory Memory

UART

DMA

SPI

Virtual Platform

INTC

USB

VIO VIO

SPI flash

CPU

Wrapper

IP RTL

May 9, 2016 15

Host PC SDL

multimedia Lib

• Virtual Platform

− Linux Video playback

Demo

ARM

CA9

TLM

memory memory memory UART

DMA SSP

Virtual Platform

LCDC

3.3 Kernel

Application mplayer

Cortex-A9 BSP

DMA driver

SSP driver

LCDC driver

Sound

Display

Host PC

May 9, 2016 16

• Virtual Platform Solution

− Next generation software development

− Shift left the schedule

− Flexible prototyping solution with FPGA & RTL

Simulation

Summary

Virtual Prototyping Hybrid Prototyping RTL Co-Simulation

TLM

memory memory Memory

UART

DMA

SPI

Virtual Platform

INTC

USB

VIO VIO

SPI

flash

CPU

SDC

SD

card

TLM

memory memory Memory

UART

DMA

SPI

Virtual Platform

INTC

USB

VIO VIO

SPI

flash

CPU

wrapper

IP RTL

memory

TLM

memory Memory

USB Transactor

Virtual Platform

CPU

UART

DMA

May 9, 2016 17

Thank you

Ken Liao, Senior Associate VP, Faraday