Unit 6 assembly language programming

UNIT 6 – Assembly Language Programming

Prof. K. U. Sharma

Introduction

• An interrupt is an event which informs the CPU that its

service (action) is needed.

• Sources of interrupts:

– internal fault (e.g.. divide by zero, overflow)

– software

– external hardware :

• maskable

• nonmaskable

– reset

4/5/2014 Prof. K. U. Sharma, PRMCEAM, Contact: karthik8777@gmail.com, 9096996329

Interrupt Terminologies

• Interrupt pins: Set of pins used in hardware interrupts

• Interrupt Service Routine (ISR) or Interrupt handler: code used for

handling a specific interrupt

• Interrupt priority: In systems with more than one interrupt inputs,

some interrupts have a higher priority than other

– They are serviced first if multiple interrupts are triggered

simultaneously

• Interrupt vector: Code loaded on the bus by the interrupting device that

contains the Address (segment and offset) of specific interrupt service

routine

• Interrupt Masking: Ignoring (disabling) an interrupt

• Non-Maskable Interrupt: Interrupt that cannot be ignored (power-

Interrupt Vectors

• The processor uses the interrupt vector to determine the address of the ISR of

the interrupting device.

• In the 8088/8086 processor as well as in the 80386/80486/Pentium processors

operating in Real Mode (16-bit operation), the interrupt vector is a pointer to

the Interrupt Vector Table.

– The Interrupt Vector Table occupies the address range from 00000H to

003FFH (the first 1024 bytes in the memory map).

– Each entry in the Interrupt Vector Table is 4 bytes long:

• The first two represent the offset address and the last two the segment

address of the ISR.

– The first 5 vectors are reserved by Intel to be used by the processor.

• The vectors 5 to 255 are free to be used by the user.

Basic Procedure for Processing Interrupts

• When an interrupt is executed, the mp:

– finishes executing its current instruction (if any).

– saves (PUSH) the flag register, IP and CS register in the stack.

– goes to a fixed memory location.

– reads the address of the associated ISR.

– Jumps to that address and executes the ISR.

– gets (PULL) the flag register, CS:IP register from the stack.

– continues executing the previous job (if any).

8088/86 Hardware Interrupts pins

INTR: Interrupt Request.

– Input signal into the CPU

– If it is activated, the CPU will finish the current instruction and respond with

the interrupt acknowledge operation

– Can be masked (ignored) thru instructions CLI and STI

• NMI: NonMaskable interrupt.

– Input signal

– Cannot be masked or unmasked thru CLI and STI

– Examples of use: power frailer. Memory error

• INTA: Interrupt Acknowledge.

– Output signal

The Interrupt flag

• IF (Interrupt Enable Flag) D9: used to mask any hardware interrupt

that may come in from the INTR pin.

• When IF=0, all hardware interrupt requests through INTR are masked.

• This has no effect on interrupts coming from the NMI pin.

• CLI sets IF to 0, STI sets IF to 1.

Block Diagram of 8259

8259 Interrupt IC

• It can manage 8 – priority interrupts, which is equivalent to provide 8 –

interrupt pins on a processor instead of single INTR pin.

• By cascading number of 8259 IC’s, it is possible to generate more than 8 –

interrupts.

• Due to the availability of IMR (Interrupt Mask Register), it is possible to

mask any or all the interrupt request to 8259.

1. Data Bus Buffer:

• This block is used to write control word or to read the status value. It is

bidirectional 8-bit buffer which is also used to send the address of the ISR.

4/5/2014 Prof. K. U. Sharma, PRMCEAM, Contact:

karthik8777@gmail.com, 9096996329

8259 Interrupt IC

2. Read/Write Control Logic:

• This block comprises of various control signals such as RD, WR, A0, CS.

The RD/WR control signal are used for read/write operation, whereas A0

address line is used to select the different command words as shown

below.

A0 Control Word Kinds of Control

0 ICW ICW1 (A0 = 0)

ICW2 (A0 = 1)

ICW3 (A0 = 1)

ICW4 (A0 = 1)

1 OCW OCW1 (A0 = 1)

OCW2 (A0 = 0)

OCW3 (A0 = 0)

8259 Interrupt IC

• Out of these above command words, ICW1 & ICW2 are compulsory,

whereas others are optional taken as and when required.

3. Cascade Buffer:

• In order to expand various interrupt levels, 8259 can be cascaded with

various other 8259 IC’s. This cascade buffer generates necessary control

signals for cascade (master/slave) operation of 8259.

• Here SP/EN is connected to +Vcc for mater, otherwise grounded for

slave.

8259 Interrupt IC

4. Registers:

i. IRR (Interrupt Request Register):

• An IRR is used to store the interrupt level which is requesting for

interrupt service. The 8 interrupt input sets the corresponding bits in

IRR as shown below.

1: Interrupt Request

0 : No request

IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

8259 Interrupt IC

ii. IMR (Interrupt Mask Register):

• An IMR stores the masking bit pattern for the interrupt level to be

masked or ignored. This register can be programmable by using

OCW1 of 8259.

• The structure of IMR is as shown below.

1: Respective Interrupt Mask (ignore)

0 : Respective Interrupt Unmask (accept)

IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

8259 Interrupt IC

3. ISR (Interrupt Service Register):

• It gives the status of current interrupt level being serviced by the

microprocessor.

• The microprocessor executes an ISS (Interrupt Service Sub Routine)

program in response to each interrupt, it means the processor will be

giving service to only single interrupt at a time.

4. Priority Resolver:

• It determines the priorities of different interrupts requested inside

IRR. Depending upon the priority set as Fixed type, a higher priority

interrupt is selected by the resolver.

• While forwarding that interrupt to the processor, the PRL also

monitors IMR and ISR.

8259 Interrupt IC

5. Interrupt Control Logic:

• This block will forward an interrupt request from 8259 to 8086, in

response to which the processor gives an acknowledgement through

• This INTA shows an acceptance of the interrupt by the processor.

Priority Modes of Intel 8259

• Intel 8259 can be operated in one of the following mode as:

1. Fully Nested Mode (FNM) / Default Mode.

2. Special Fully Nested Mode (SFNM).

3. Special Mask Mode (SMM).

4. Rotating Priority Mode

1. Automatic Rotation

2. Specific Rotation

5. Polled Mode.

Command Words of Intel 8259

• There are 2 types of command words available in 8259

1. Initialization Command Word (ICW)

2. Operational Command Word (OCW)

• Bit D0 is used to specify the need of ICW4, if this bit is set to 0, then

ICW4 is not needed and vice versa.

• Bit D1 is used to specify whether single 8259 is used or 8259 is

operated in cascade mode.

• Bit D2 is used to specify an address interval between two successive

ISS location either separated by 4 byte or 8 byte.

• Bit D3 is used to initiate an interval either level triggered or edge

triggered.

• Bit D4 is permanently kept at logic 1 whereas D5, D6 & D7 are

undefined.

• This is used to specify a 8 bit pointer value for address of different ISS.

• This address is given from INT0 to INT7, here bit D0 to D2 are used to

specify an interrupt level.

• Whereas bits D3 to D7 are used to specify an ISS pointer value for

each interrupt level.

• Therefore A11 … A15 will give 25 = 32 address values for each

interrupt levels, and hence 32*8 = 256 address values can be given for

all interrupts of 8259.

• There are two types of ICW3 used in cascade configuration, it means

in case of single 8259 there is no need of ICW3.

1. ICW3 for Master

2. ICW3 for Slave

ICW3 for Master :

• In the format shown above, the presence or absence of various slaves

is provided by writing logic 1 or logic 0 respectively.

• If slaves are connected then respective bit must be set to logic 1.

ICW3 for Slave:

• This is used to provide slave ID. This slave ID or address is provided

through D0, D1 & D2.

• The remaining bits are kept at logic 0.

• It is an optional command word in which bit D0 is used to specify the

microprocessor used.

• Bit D1 is used to implement AEOI or EOI.

• Bit D2 & D3 are only used during master/slave configuration whereas

bit D4 is used for SFNM or FNM. Others are always 0.

Initialization Sequence of 8259

Operational Command Words

Problems:

1. Specify the value of ICW1 needed to configure an 8259 as follows:

ICW4 not needed, single device interface and edge triggered inputs.

2. Specify the value of ICW4 such that the 8259 is configured for use in

8086 system, with normal EOI, buffered mode master and SFNM

mode disabled.

Answers:

x x x 1 0 x 1 0

0 0 0 0 1 1 0 1

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