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Product PreviewZL30102/5
REDUNDANT SYSTEM CLOCK SYNCHRONIZER DPLLs
The ZL™30102 and ZL30105 are high-performance digital phase-locked loops
(DPLLs) designed for synchronization and timing control of redundant system clocks
requiring Stratum 4/4E and Stratum 3 or SDH timing specifications, respectively.
The ZL30102/5 are based on an enhanced DPLL architecture that ensures an easy
and cost-effective route to compliance, with industry-standard synchronization clock
interfaces. Featuring clock redundancy, low jitter generation, and excellent holdover
accuracy, the ZL30102/5 provide the critical synchronization and sourcing functions
in access and enterprise premises equipment to carrier-class levels.
The ZL30102/5 provide timing solutions meeting Telcordia requirements for
enterprise equipment using T1/E1 interfaces and high-performance H.110 buses.
In addition, the ZL30105 is suited for PDH/SDH network equipment that requires
a redundant ultra-low jitter 19.44 MHz timing backplane such as Advanced TCA™
(Telecommunications Computing Architecture).
ZL30105 Simplified Block DiagramT1/E1/SDH Stratum 3 Redundant
System Clock SynchronizerIndependent
Input ReferencesStratum 3
Core Digital PLLClock and Frame
Pulse Outputs
Reference Switchingwith Phase Transient
Suppression
Jitter and Wander Filtering
Selectable LoopFilter Bandwidth
High AccuracyHoldover (0.01 ppm)
RedundantReference and Framing Pulse
2, 8 kHz, 1.5, 2, 8, 16 or 19 MHz
Hardware Control and Advanced MonitoringManual or Automatic Reference Switching
Reference Monitoring with selectable out of range frequency limits
PrimaryReference
8 kHz, 1.5, 2, 8 or 16 MHz
SecondaryReference
2, 8 kHz, 1.5, 2, 8, 16 or 19 MHz
T1/E12 and 8 kHz
1.5, 2, 3, 4, 8,16, 32, 65 MHz
Programmable6,8.4,34, 44 MHz
SDHUltra Low Jitter
(<20 psRMS)2 kHz, 19 MHz
8 ClockOutputs
4 Frame Pulses Outputs
20 MHz Osc./xtal
Control and Monitoring
Low Jitter
RedundantClock and Sync Inputs
ReferenceClockInputs
Applications
• ClockandframepulsesourceforAdvanced1TCA,H.110,CT-BUS,ST-BUS,GCI,andotherTDMbuses
• Synchronization and timing control for multi-trunk T1/E1 and SDH systems, such asDSLAMs,mediagateways,wirelessbasestations,andIP-PBXs
• 8kHzclockmultiplier
1.ZL30105only
Enhanced Features for PDH and SDH Redundant Clock Interface
• Accepts three reference clocks thatsynchronize to any combination of 2 kHz, 8kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz,16.384MHzand19.4411MHz
• Reference clock and synchronization pairinputs provides redundancy switching withclosephase alignment betweenprimary andsecondarysystemclocks
• Advancedreferencemonitoringwithselectableclockfrequencyrangeprovideslock,holdover,andout-ofrangeindications
• Simple hardware control interface offersmanual or automatic hitless referenceswitching
• ZL30105highperformanceDPLLfeatures:
- Ultra-low jitter of less than 20 psRMS on the 19.44 MHz clock exceedingGR-253-COREOC-3andG.813STM-1specifications
-Lessthan600psp-pintrinsicjitteronalltheotherclockandframepulseoutputs
-Accurateholdoverperformanceof0.01ppm
- Generates a wide range of fixed and programmable clock and frame pulseoutputsforPDHandSDHsystems
Standards Compliant
• ANSIT1.403andETSIETS300011forISDNprimaryrateinterfaces
• ITU-T G.823 for 2048 kbps and G.824 for1544kbpsinterfaces,G.8131option1
• TelcordiaGR-1244-COREStratum 4/4E andStratum31
Complementary Microsemi Products
• APLLandDPLLforSONET/SDH
• TDM/TSIswitchesandT1/E1transceivers
Customer Support
The ZL30102/5 are supported by a customerevaluation board and the network of in-housefield application and design engineers ofMicrosemi.
Microsemi Corporate HeadquartersOneEnterprise,AlisoViejoCA92656USAWithintheUSA:+1(949)380-6100Sales:+1(949)380-6136Fax:+1(949)215-4996
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductorsolutions for: aerospace, defense and security; enterprise and communications; and industrialand alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com.
ZL30102/5
©2012MicrosemiCorporation.Allrightsreserved.MicrosemiandtheMicrosemilogoaretrademarksofMicrosemiCorporation.Allothertrademarksandservicemarksarethepropertyoftheirrespectiveowners.
PublicationNumber:PP5877
Networkingequipmentdeployedincentralofficesandcustomerpremisesmustmeetstrictinternationalstandardsfortimingandsynchronizationtoensureaccurateandreliablesystemperformance.TheZL30102/5DPLLsprovideacompleteoff-the-shelftimingsolutionfornetworkingequipmentcarryingcircuit-switchedandpacket-basedtraffic.
ThefollowingdiagramdescribesanAdvancedTCA™centralizedtimingconfiguration thatcanbeusedwithanybackplanedatabusorswitchfabricconfiguration.TheZL30105ontheprimaryandsecondarytimingcard each provide reliable, phase-aligned, low jitter 8 kHz, and 19.44MHzsystemclockstoallthelinecardsconnectedtothebackplane.
Theprimary timingcard isusuallysynchronized toaBITS,SSUclock,oranextractednetworktimingreferencesignalfromthelinecards.TheZL30105acceptsawide rangeofstandard referenceclockand framepulse frequencies.Each reference input ismonitoredwithin itsspecificfrequency range and maximum frequency deviation limits. When thenetwork frequencies are outside the programmable frequency range,
theZL30105providesautomaticreferenceswitchingbetweenreferenceinputswithoutanydisruptiontotheprimarysystemclockoutputs.Whenbothnetworkreferencesaredown,theZL30105’sholdovermodekeepsthe primary system output clocks accurate within 0.01 ppm of thepreviousvalidreference.
On the secondary timing card, the ZL30105 is synchronized to theprimarysystemclockusingthereferenceclockandsynchronizationpairinputstoprovideredundancyswitching.Precisephasealignmentoftheprimaryandsecondarytimingcardsclockoutputsisachievedunderalljitterandwanderconditions.Thisenablesthelinecardstoswitchatanytimebetweenprimaryandsecondarysystemclockswithoutdisruptionorlossofsynchronization.
The ZL30102 and ZL30105 DPLLs enable designers to easily andcosteffectively built redundant timing systems thatmeet Telcordia andSDHtimingrequirementsforAdvancedTCAandH.110backplanes.
RedundantSystemClockSynchronizerDPLLs
Applications
Centralized Clock Timing Advanced TCA Backplane ApplicationPrimary (Master) System Clock Timing Card
T1/E1/SDHSTratum 3Redundant
System ClockSynchronizer
ZL30105
Any Frequencies2, 8 kHz1.5, 2 ,8,
16 or 19 MHz
Synchronized to Network Reference
Clock InputsPrimary
Clock Outputs
19.44 MHz
8 kHz
Master Clock Control andReference Monitoring
20 MHz ClockOscillator
T1/E1/SDHSTratum 3Redundant
System ClockSynchronizer
ZL30105
System Line Cards
Advanced TCA Backplane
Secondary (Slave) System Clock Timing Card
Timing Buses Data Bus
Synchronized to Redundant Clockand Sync Inputs
from Master Clock
Slave Clock Control andReference Monitoring
20 MHz ClockOscillator
Frequency and Phase AlignedPrimary andSecondarySystem Clocks
Selected ClockSource
Redundant ClockSource
PrimarySystemClocks
NetworkReference
Clocks
SecondarySystemClocks
19.44 MHz
8 kHz
SecondaryClock Outputs
Timing Interface
Line CardProcessing
Data Interface
Any SwitchFabric
Architecture
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