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CURRICULUM
VLSITECHNOLOGYSYSTEM VERILOG WITH TCL
Six Week Industrial Training on Advanced VLSI-Verification using SystemVerilog and basic scripting
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Course Type - Hands-on TrainingDuration - 6 weeks(Including week-off)Eligibility- BE/BTech/ME/MtechPrerequisite - Digital,Verilog and CTool - Modelsim ,Questasim
Course content
Verification concepts in VLSI
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VLSI Design FlowThe Verification Process The Verification Methodology Basic Testbench Functionality Directed Testing Methodology Basics Testbench Components Layered Testbench Building a Layered Testbench Simulation Environment Phases Verification Flow in VLSIVerification domains and toolsWhat is bug?Bug tools introduction etc.
System Verilog Basics
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Introduction to systemVerilogSystemverilog Advantages over verilog and VHDLUse of system verilog in Industries and for DesignWhy SV for Verification?Data TypesOperatorsKeywordsArraysQueueNew constructs in SVTasks and FunctionsExperiments on each constructs on lab
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SOUTH EXTENSION
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Plot No. 366, 2nd Floor, Kohat Enclave, Pitampura,( Near- Kohat Metro Station)Above Allahabad Bank, New Delhi- 110034.
Noida - 201301, (U.P.) INDIA 70-70-90-50-90 +91 99-9999-3213 70-70-90-50-90 70-70-90-50-90
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+91 98-1161-2707
(DELHI)
System Verilog for verification
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Object oriented paradigm (OOPs) – class introduction & inheritanceTask Functions and Void FunctionsProcedural statements and routinesCreating new ObjectsMemory allocationWriting verification environment
Basic Scripting using Tcl
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IntroductionData types, variables, assignments and expressionsLists, arrays and associative arraysSubroutines or ProceduresControl structuresFile Input and OutputThe world of regular expressionsMore on TCL - trace, eval, exec, info, history, format
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