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Dr. Ahmed H. Madian-VLSI 1
Very Large Scale Integration (VLSI)
Dr. Ahmed H. Madian Ah_madian@hotmail.com
Lecture 6
Dr. Ahmed H. Madian-VLSI 2
Contents
Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell Technology FPGA Technology
Dr. Ahmed H. Madian-VLSI 3
Gate Arrays and Sea-of-Gates
This means to construct a common base array of transistors and personalize the chip by altering the metallization (metal and via masks) that is placed on top of the transistors.
Dr. Ahmed H. Madian-VLSI 4
Gate Arrays Technology
prefabricated wafers I/O stages predefined
regular array of fets and interconnection channels
interconnection defines functionality
features size: 100 - 1M gates
short turn around time
cheap at medium quantities
Unsuitable for regular structures like RAM, PLA, ALU
Gate Array — Sea-of-gates
rows of
cells
routing channel
uncommitted
VDD
GND
polysilicon
metal
possiblecontact
In1 In2 In3 In4
Out
Uncommited
Cell
Committed
Cell
(4-input NOR)
Dr. Ahmed H. Madian-VLSI 5
Dr. Ahmed H. Madian-VLSI 6
Sea-of-Gate Technology
prefabricated wafers I/O stages predefined regular array of fets, no
reserved interconnection channels
interconnection defines functionality
features size: 100 - 1M gates short turn around time cheap at medium quantities suitable for regular structures
like RAM, PLA, ALU
Dr. Ahmed H. Madian-VLSI 7
Standard Cell Technology
complete fabrication process predefined library of base
functions
modular similar to TTL families
features chip size limits complexity
cheap at high quantities
standardized cell height
unsuitable for regular structures
more flexible and compact than gate array
Standard cell layout
Layout made of small cells: gates, flip-flops, etc.
Cells are hand-designed.
Assembly of cells is automatic:
cells arranged in rows;
wires routed between (and through) cells.
Dr. Ahmed H. Madian-VLSI 8
Guidelines to Creating a Standard Cell Library
Vertical and Horizontal Routing Grids:
- Cell pins, with the exception of abutment pins (VDD and GND) must be placed on the intersections of the vertical and horizontal routing grids.
- Vertical and horizontal routing grids may be offset with respect to the cell’s origin, provided that the offset distance is exactly one-half of the grid spacing.
- The cell height must be a multiple of the horizontal grid spacing; the cell width must be a multiple of the vertical grid spacing.
Dr. Ahmed H. Madian-VLSI 9
Figure 1: Horizontal Routing Grid Examples
Horizontal Grid Spacing
(a) Without Offset
One-half Horizontal Grid Spacing
One-half Horizontal Grid Spacing
Horizontal Grid Spacing
(b) With Offset
Cell Origin
Dr. Ahmed H. Madian-VLSI 10
Figure 2: Vertical Routing Grid Examples
(a) Without Offset (b) With Offset
Vertical Grid Spacing One-Half Vertical Grid Spacing
Cell Origin
Dr. Ahmed H. Madian-VLSI 11
Figure 3: Sample Standard Cell Routing Grid
(a) Without Offsets (b) With Vertical and
Horizontal Offsets
Dr. Ahmed H. Madian-VLSI 12
Standard cell structure
VDD
VSS
n tub
p tub
Intra-cell wiring
pullups
pulldowns
pin
pin
Fee
dth
rough a
rea
Dr. Ahmed H. Madian-VLSI 13
Standard cell design
Pitch: height of cell.
All cells have same pitch, may have different widths.
VDD, VSS connections are designed to run through cells.
A feedthrough area may allow wires to be routed over the cell.
Dr. Ahmed H. Madian-VLSI 14
Cell Design
Standard Cells General purpose logic
Can be synthesized
Same height, varying width
Datapath Cells For regular, structured designs (arithmetic)
Includes some wiring in the cell
Fixed height and width
Dr. Ahmed H. Madian-VLSI 15
What are Routing Grids For?
• The routing grids are where the over-the-cell metal routing will be routed.
• The pins of your standard cells should always lie on the intersections of the horizontal and vertical routing grids. Although some CAD tools will route to off-grid pins, this may cause some other complications.
Dr. Ahmed H. Madian-VLSI 16
Single-row layout design
Routing channel
cell cell cell cell cell
cell cell cell cell cell
wire Horizontal track Vertical track
height
Dr. Ahmed H. Madian-VLSI 17
Routing channels
Tracks form a grid for routing.
Spacing between tracks is center-to-center distance between wires.
Track spacing depends on wire layer used.
Different layers are (generally) used for horizontal and vertical wires.
Horizontal and vertical can be routed relatively independently.
Dr. Ahmed H. Madian-VLSI 18
Routing channel design
Placement of cells determines placement of pins.
Pin placement determines difficulty of routing problem.
Density: lower bound on number of horizontal tracks needed to route the channel.
Maximum number of nets crossing from one end of channel to the other.
Dr. Ahmed H. Madian-VLSI 19
Pin placement and routing
before
a b c
b c a
before
a b c
b c a
Density = 3 Density = 2
Dr. Ahmed H. Madian-VLSI 20
Example: full adder layout
Two outputs: sum, carry.
sum
carry
x1
x2
n1
n2
n3
n4
Dr. Ahmed H. Madian-VLSI 21
Layout methodology
Generate candidates, evaluate area and speed.
Can improve candidate without starting from scratch.
To generate a candidate:
place gates in a row;
draw wires between gates and primary inputs/outputs;
measure channel density.
Dr. Ahmed H. Madian-VLSI 22
A candidate layout
x1 x2 n1 n2 n3 n4
a
b
c
s
cout
Density = 5
Dr. Ahmed H. Madian-VLSI 23
Improvement strategies
Swap pairs of gates.
Doesn’t help here.
Exchange larger groups of cells.
Swapping order of sum and carry groups doesn’t help either.
This seems to be the placement that gives the lowest channel density.
Cell sizes are fixed, so channel height determines area.
Dr. Ahmed H. Madian-VLSI 24
Left-edge algorithm
Basic channel routing algorithm.
Assumes one horizontal segment per net.
Sweep pins from left to right:
assign horizontal segment to lowest available track.
Dr. Ahmed H. Madian-VLSI 25
Example
A B C
A B B C
Dr. Ahmed H. Madian-VLSI 26
Limitations of left-edge algorithm
Some combinations of nets require more than one horizontal segment per net.
B A
A B
aligned
?
Dr. Ahmed H. Madian-VLSI 27
Vertical constraints
Aligned pins form vertical constraints.
Wire to lower pin must be on lower track; wire to upper pin must be above lower pin’s wire.
B A
A B
Dr. Ahmed H. Madian-VLSI 28
Dogleg wire
A dogleg wire has more than one horizontal segment.
B A
A B
Dr. Ahmed H. Madian-VLSI 29
Rat’s nest plot
Can be used to judge placement before final routing.
Dr. Ahmed H. Madian-VLSI 30
Guidelines to Creating a Standard Cell Library
• A standard cell library must contain at least the following cells to be able to implement any function:
- NAND
- NOR
- NOT
- DFF
• Additionally, you can expand the standard cell library to include additional cells like Tie-high, Tie-low cells, I/O Pads, and multiple-input gates (e.g. a 4-input NOR gate).
Dr. Ahmed H. Madian-VLSI 31
33
Standard Cells
Cell boundary
N Well
Cell height 12 metal tracks Metal track is approx. 3 + 3
Pitch = repetitive distance between objects
Cell height is “12 pitch”
2
Rails ~10
In Out
V DD
GND
Dr. Ahmed H. Madian-VLSI
34
Multi-Fingered Transistors One finger Two fingers (folded)
Less diffusion capacitance
Dr. Ahmed H. Madian-VLSI
Standard cell
Dr. Ahmed H. Madian-VLSI 35
Datapath Layout Example: Adder
Standard cell layout
Bit-slice cell layout
Dr. Ahmed H. Madian-VLSI 36
Arithmetic and Logic Unit (ALU)
Functions
Arithmetic (add, sub, inc, dec)
Logic (and, or, not, xor)
Comparison (<, >, <=, >=, !=)
Control signals
Function selection
Operation mode (signed, unsigned)
Output
Operation result (data)
Flags (overflow, zero, negative)
Dr. Ahmed H. Madian-VLSI 37
Architecture of a CPU
Flags: overflow, zero, etc.
Read/write
Mem
Control
Data path Register
File
Dr. Ahmed H. Madian-VLSI 38
Simple ALU Example
Tile identical processing elements [© Prentice Hall]
Bit 3
Bit 2
Bit 1
Bit 0
Regis
ter
Ad
der
Shif
ter
Mult
iple
xer
Data
in
Data
Out
Control
Dr. Ahmed H. Madian-VLSI 39
Dr. Ahmed H. Madian-VLSI 40
Macrocell Technology
complete fabrication process combines semi- and full custom
technologies
predefined library of base functions
generators for regular structures
features chip size limits complexity
short design, long fabrication time
cheap at high quantities
high flexibility, compact layouts
Dr. Ahmed H. Madian-VLSI 41
Full Custom Technology
complete fabrication process
total flexibility, only limited by layout rules
manual design
features
chip size limits complexity
long design and fabrication time
efficient use of silicon area
cheap only at highest quantities (ex. uP, memories, ...)
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