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Ultra Low Current Input Analog to Digital Converter based Bio-Chemical Sensor and Interfacing Circuit
Abstract- A study of real time biological phenomenon especially at intra-cellular levels mandates usage of non-obtrusive probing and measurement techniques. It is imperative that the phenomenon being observed should not be disturbed in its dynamics and the sensor dimensions should be small enough not to damage cellular integrity. Usage of micro needle tungsten electrode sensors and amperometry techniques is one of the acceptable methods to design sensors for such measurements. In this paper we present amperometry based sensor circuit for measurement of ultra-low currents. Based upon established theory sensing circuits are analyzed and designed for measuring bio-chemical phenomenon occurring at rates of >10ms. The currents involved in these analyses fall in the range of a few Pico-amperes. Based upon these requirements we achieved an analog to digital converter with input current resolution of ~100pA and a dynamic range of 100pA-1.5uA. The ADC output is coupled via a RF transmitter to enable walk-in readouts from the sensor. In addition, a potentiostat circuit is also presented. The whole system is integrated in AMI 0.5um process for a single System-On-Chip solution.
I. INTRODUCTION
io-Chemical sensors are devices that detect physiological change or changes in the chemical/biological composition of materials in the environment. They usually consist of a
sensitive layer or coating and a transducer. Quoting Dr. Jiri Janata, “Upon interaction with a chemical species (absorption, chemical reaction, charge transfer, etc.), the physiochemical properties of the coating, such as its mass, volume, optical properties, or resistance, etc. reversibly change. These changes in the sensitive layer are detected by the respective transducer and translated into an electrical signal such as frequency, current, or voltage, which is then read out and subjected to further data treatment and processing.” In accordance with the principles laid out by Dr. Janata, chemical sensors can be classified into four principle namely Chemo-mechanical, Thermal sensors, Optical sensors and Electrochemical sensors. Our research focuses on designing an ultra-sensitive electrochemical sensor interface circuitry. In January of 2009, the U.S. government passed the American Recovery and Reinvestment Act (ARRA) sanctioning $ 10.4 billion to the NIH for stimulating and accelerating the pace of biomedical research. A big part of this grant would focus on neural research programs. Dr. Story Landis, Director of the National Institute of Neurological Disorders and Stroke (NINDS) in her address to the nation said, “Basic research pursues an understanding of the normal
and abnormal structure and activities of the human nervous system. The knowledge gained from this research creates the foundation for diagnosing and treating brain disease. Some important areas of NINDS basic research include: biology of the cells of the nervous system, brain and nervous system development, genetics of the brain, cognition and behavior, neuro-degeneration, brain plasticity and repair, neural signaling, learning and memory, motor control and integration, sensory function, and neural channels, synapses, and circuits. The great challenge of modern neuroscience is to translate the remarkable findings of basic science into useful therapies for those who suffer the devastating effects of neurological disorders.”
Our research goal here is to develop technology for neuroscience research. In particular, we are interested in sensing neuro-chemicals at single neuron and single synapse level. Such unprecedented sensitivity would allow fundamental studies of distribution of neuro-chemicals in neural networks.
Figure 1: Focus of our Research
Understanding brain functionality on a fundamental level
requires measurements of both electrical and chemical neural activity. Implantable, bio-compatible, robust, multi-functional micro-probes capable of electro-physiological and chemical sensing in the brain are becoming available. These sensors detect electro-physiological phenomenon that generate current in order of a few Pico-amperes. Thus mandating a low-noise, highly sensitive measurement of electrical action potentials and neuro-chemical signals.
Amanpreet Singh, Gopal B. Iyer, Abhilash Goyal, and Saravanan T. K
B
Figure 2. Block level description of Proposed System
We propose a low-power micro-system with a small form-
factor detection circuit that measures these variations reliably.
II. ANALOG FRONT END
One of the standard methods for interfacing, biological
recognition elements (BRE) to electronics utilizes classical
amperometry. The key electronic component for electro-
chemical measurement is a potentiostat which can be
configured for potentiometric (apply fixed current and
measure output voltage) or amperometric (apply fixed voltage
and measure output current) readout. In this approach, detector
sensitivities in the range of a few Pico-amperes to nano-
amperes is required. Key element is a low-level current
detection circuit with good noise performance and high
linearity over the range of inputs.
Below is a summary of the various approaches explored for
the Analog Front End (AFE) of the chemical biosensor system
Ref. Implementation Methodology
[4] Threshold voltage change in the Organic pFET
portion of CHEMFET
[5] Resistance change using Chemiresistors
[6] MOS operated in Deep-Sub threshold regime
(negative bias) – Femto-Ampere Current Mirror, FCG,
FCMA and FCR.
[7] Frequency based – by modifying the frequency of a
precision ultra-low current sawtooth oscillator.
[8] Weak inversion operation of Ion-Sensitive Field
Effect Transistor (Vth modulations)
[9] Translinear circuits – Logarithmic Amplifiers, using
MOSFETs in sub-threshold operation
[10] Capacitive sensing of input voltage with ultra-low
input referred noise
[11] Translinear (log-domain) Integrator based in Floating
Gate MOS devices
Table 1. List of used References
Figure 3: Wireless Chemical Sensor Interface System
Periodic sampling at rates more than twice the Nyquist rate
does not introduce signal distortion rather signal quantization
does. The fundamental application of over-sampling delta-
sigma modulators is to reduce this distortion. Oversampling
converters can use simple and relatively high-tolerance analog
components but require fast and complex DSP processing.
They modulate analog input into a simple digital code usually
a single bit at the oversampling rate. A trade-off between
sampling resolution and amplitude resolution can be made to
achieve relatively high resolution analog to digital converters.
In theory quantization noise of a single bit ADC is generally
expressed as,
= ∆
,
Using over-sampling the in-band quantization noise can be
reduced by square root of the OSR (Over Sampling Ratio),
=
,
By using a first order sigma-delta modulator fig.4
quantization-noise can be shaped to achieve a further
D Q
CLK
Clk Ext
Test Signal
Generator
Analog Sensor Front End
RF Transmitter Front End
Potentiostat +
Chemical Sensor
Comparator
Integrator
Figure 6. Current DAC
Figure 7. Operational Amplifier used in Integrator
Figure 8. Preamplifier – Comparator Stage I
Figure 10. Metastability removal – Comparator Stage III
Figure 9. Regenerative Latch – Comparator Stage II
Figure 11. – Slow Buffer & Edge timing circuit
Figure 12. Current Reference
Figure 13. Voltage reference using BGR
Figure 14. Folded Cascode Opamp used in BGR
reduction in the quantization error within the signal band. The
transfer function of a first-order quantizer is given in (Eq I.)
Figure 4: A First order ∆-∑ modulator.
= + ( − ) - (Eq I)
Which indicates that a ∆-∑ modulator modifies the in band
noise spectrum, the modified noise spectral power is described
as =
(2) , where τ is sampling clock period.
The modulator therefore acts a low-pass filter for the input
signal and high-pass filter to the quantization noise as shown
in fig.5. This helps in reducing the in-band distortion
introduced by the quantization process which makes a ∆-∑
ADC optimum for this application.
Figure 5: STF and NTF plots for a ∆-∑ modulator.
In a low power regime carrying information in a current mode
is more favorable than voltage mode [24]. When, the circuits
are current-driven, thus with a high impedance, the equivalent
input noise current is mainly determined by the input noise
current of the input stage. Since the equivalent input noise
current of transistors is proportional to the bias current, this
call’s for small bias currents, which is in line with the low-
power requirement. Therefore it’s favorable to choose current
as the information-carrying quantity. This explains our choice
of using current input ∆-∑ ADC in contrast to the more
pervasive designs using a voltage input signal. Also at system-
design level the choice of amplification-stages is mandate by
the same specification i.e. noise. Therefore we use a low noise
Op-Amp at the integrator stage itself so that a good SNR can
be maintained throughout the ADC chain.
III. CIRCUITS
Current DAC
Current DAC forms the front-end circuit of the ADC along
with the integrator as shown in Fig.2; coupling input signal
into the internal dynamics of the system. Essentially current
summation (∑) and subtraction (∆) functionality is achieved
through the Integrator and Current DAC blocks. And the
comparator circuit forms the real analog to digital convertor.
The current DAC receives a differential logic signal from the
comparator and converts it to an equivalent charge remove or
dump operation over the integrating capacitor.
Therefore the accuracy of these circuits determines the
systematic error that is added into the ∆-∑ loop excluding the
effects of signal quantization. To achieve the desired
precision the current source in the current DAC shown in
Figure 18 should match within 1% to remove any unwanted
offsets and the noise introduced into the system by switching
these currents in the DAC should also be minimized. The
current DAC achieves soft switching of currents by avoiding
starvation of the current sources through through current
steering.
In the current DAC for this reason the switching transistors
were kept symmetrical in the layout and the transition pulses
on the switches were slewed slowly to reduce the amount of
charge injection into the integrator through the current DAC.
These techniques help in reducing the described offsets and
inaccuracies in measurement and render accurate
measurement of small input signals.
Integrator
In the sensing circuit, integrator plays a very important role
as it integrates sensor current (modulated with the reference
current) into a voltage, which is used by the comparator to
generate a digital output. For efficient operation of this
sensing circuit, input referred noise of the Op-Amp should be
very low (in range of nV/Sqrt(Hz)), so that the noise generated
by the Op-Amp does not corrupt the input current. By
ensuring rail to rail operation of the Op-Amp enhances system
reliability even in the presence of systematic or random
offsets.
To achieve rail to rail operation its necessary to use
complementary input stages. The design hits a road block in
mid range when both the input stages would turn on leading to
twice the normal transconductance. This is generally a 3 dB
gain variation across the input common mode range. To
minimize gain variation, current-stealing topology has been
used. Here, as input common mode voltage increases, tail
current is stolen from PMOS input pair and is channeled as
bias current to NMOS differential pair. This ensures either
PMOS or NMOS input pair in ON. While in the input region
where both PMOS and NMOS pairs are simultaneously ON,
the resultant tail currents for PMOS or NMOS varies while
keeping the total biasing current constant. Thereby,
maintaining the composite transconductance of the amplifier
nearly constant over the entire ICMR.
Parameters Value
DC Gain 86.6 ~ 87.6 dB
ICMR 0.2 – 3.1 V
CMRR >120 dB
Phase Margin > 60 deg
Unity Gain BW 2.8 MHz
Input referred Noise < 45 nV/sqrt(Hz)
DC Power 190 uW
Table 2. Performance Specifications of Opamp
Using this approach gain variation of the Op-Amp across
the corners has been reduced to less than 1.2 dB. The input-
referred thermal noise power is inversely proportional to
transconductance of the input pair [25]. Since flicker noise or
1/f noise, is a major concern for a low-noise low-frequency
circuit, we minimize the effect of both these noise sources by
using PMOS transistors as input devices and by using devices
with large gate area we were able to reduce the input referred
noise of the Op-Amp to 30 nV/sqrt(Hz). The schematic of the
Op-Amp is shown in fig 7. Common-centroid technique has
been used in layout and the summary of results obtained after
post-layout simulation across process corners are given in
Table 2. The noise performance is shown in fig.18.3.
Comparator
The comparator is a key block in the delta-sigma loop. It
has been implemented as a clocked comparator for conserving
power. However switching introduces kickback noise that can
find its way back to the sensor. The device sizing was adjusted
and additional buffering was done to ensure that the
detrimental effects of kickback noise are minimized.
The fig8 shows the first stage comparator. The circuit
consists of an input differential pair and a latch pair, both
sharing the diode connected MOS load. Unlike a MOS triode
region resistor, this diode largely decouples the signal gain
and output common-mode voltage. The non-linearity of the
diode load can affect the zero-crossing offset at the output.
In the reset mode, CLK is low and the differential output
follows the differential input. While the comparator’s input is
being sampled to its output, a shorting switch (to the right)
lowers the first comparator voltage gain to less than one and
erases the memory of previous decision. Ideally a short pulse
(about 10% of the CLK period) should be used to reset and
erase memory. However that would lead to additional circuitry
on the clock distribution network. To minimize that and
conserve power we explore the use of Inverted_CLK on the
switch. Fixed Gain-Bandwidth product implies that the low
voltage gain during the comparator’s reset mode gives a high
output bandwidth for fast erase. However, the gain should be
large to overcome any dynamic offset in the regenerative
latch.
The fig9 shows the second stage comparator. This second
stage provides rail-to-rail output for the D-FF or SR-latch. As
in the previous stages, the overdrive recovery time also limits
the highest frequency of operation of the delta-sigma ADC.
During reset mode, its output is reset through two parallel
discharge paths for fast overdrive recovery. In the next half
clock cycle of regeneration, differential pair NMOS
configured by cross-coupled CMOS inverters steer the tail
current from one side to the other, speeding up regeneration.
Without the tail NMOS to couple the NMOS, one output node
needs to drop its voltage from VDD to below VTH to turn off
the corresponding NMOS transistor.
Additional set of buffers have been inserted in the
comparator path to ensure removal of any meta-stability, refer
to fig10. The comparator is clocked at 0.13MHz in our system.
Voltage Controlled Oscillator
The transmitter used here comprises of a Voltage controlled
oscillator. The VCO oscillation frequency is controlled by the
Manchester Encoded data signal. As a resonant oscillator it
features an off chip inductor (68 nH) and MOS capacitor
which forms an LC tank, fixes the fundamental frequency at
433 MHz. Additional MOS capacitors are added to ensure
variable Modulation index and the flexibility is achieved by
providing a 6 bit digital tuning. IF1 to IF6 is the digital control
used in varying modulation index, which is selected by using a
3 to 8 decoder. The VCO produces a 433 MHz signal for a
logic high digital input. Based on the input the frequency of
oscillation for a logic low digital input can be spaced at a
maximum of 415 MHz. The spacing can be varied from 3 to
18 MHz in steps of 3 MHz. “Frequency pushing” is the effect
of variation of oscillation frequency with power supply. The
variation in power supply changes the effective voltage across
the MOS capacitor where in the capacitance offered also
changes there by leading to a change in oscillation frequency
with varying supply voltage.
Parameters Value
Osc Frequency 433 MHz
Tuning Range 18 MHz
Phase Noise -120 dBc/Hz
Output Power +3 dBm
DC Power 1 mW
Tuning Sensitivity 6 MHz / V
Table 3. Performance Specifications of VCO
Figure 15. VCO – FSK Modulator
Figure 16. Test Signal Generator
Figure 17. Capacitor Bank
Figure 18. Current Source / Sink Scaling Circuit for Current Steeing DAC
Chemical Sensor Interface Circuit a.k.a Potentiostat
The Potentiostat circuit is the electronic interface to a large
category of amperometric chemical sensors which are capable
of detecting many biologically and environmentally important
analytes. Amperometric sensors typically consist of three
electrodes— the Auxiliary (AE), Reference (RE) and Working
Electrode (WE). To determine the concentration of an analyte,
a known source voltage, Vsrc, is applied to the sensor between
the working and reference electrodes such that
= − =
When Vcell reaches the analyte’s redox (reduction oxidation
reaction) potential, a redox current which is proportional to the
analyte concentration, is generated at the working electrode. In
the three electrode Chemical sensor, a reference potential is
applied between the AE and WE. The sensing current is then
measured at the WE. As current application is a chemical
sensor, the electrodes are prone to oxidation and ionization
effects. This causes ionic deposition on the electrodes and
would vary the sensed current. To mitigate this effect, we need
to ensure that the applied potential (between AE and WE) is
maintained at a constant level. Hence the potentiostat circuit is
used to ensure that Vcell tracks Vsrc under varying current
loading conditions. The transfer function from Vsrc to Vcell is
given by the following equations.
The voltage swing at the sensor, ∆ is given by above
equations. These equations are valid only if the operational
amplifier swings rail-to-rail. Hence, a wide input swing rail-
to-rail, Op-Amp was implemented. The potentiostat
implementation is shown in fig16. Resistor R1 is fixed at 280
KΩ to minimize the power consumption. The Op-Amp swings
between the supply rails and has an ICMR of 0.2V to 3.1V for
a 3.3V supply. This amplifier is similar to the one used in the
integrator of the Sigma-Delta ADC. However, to minimize the
area, the PMOS input pair has been sized down,
compromising marginally on the gain and linearity. To model
potentiostat, Rs = 10Ω and Rfw = 1MΩ was assumed and
post-layout simulation results are given in fig. 16.
Reference Generators
Bandgap Reference Fig13 Voltage Generator has been
designed with the temperature coefficient of 1.75ppm/C at
TT process corner, over a temperature range of 0-80C. Over
all the process and temperature corners the maximum
variation in the reference voltage is below 5mV.
The error amplifier is a PMOS input folded-cascode
amplifier to cater to voltages below VSUPPLY-MID. The novelty
of this architecture is the elimination of the mismatch due to
PMOS transistors. In the conventional BGR topology, the
PMOS mismatch has a direct and strong influence over the
∆VBE of the PNPs. However, in the proposed architecture, the
two branches obtain their currents from the same PMOS
transistor, thus avoiding the error due to device mismatch.
DC Power 187.3µW
Temp
Coefficient
1.747ppm/C VREF-HIGH
0.860ppm/C VREF-LOW
VREF-HIGH 1.885V
VREF-LOW 942.7mV
Noise 312nV/sq.rt.Hz @ 100MHz BW
Table 4. BGR Performance Specification The current reference circuit Fig12. is essentially a
reference whose output current is independent of any PVT
(Process-Voltage-Temperature) variations. The presented
design achieves this through a CTAT-PTAT based current
summation where any variations due to temperature are
cancelled out. The design inherently relies on variations in
band-gap voltage of a BJT i.e. temperature gradient of ∆VBE
or VBE. This voltage is independent of any supply variations
and is strongly related to BJT fabrication and ambient
temperature. The variations due to process cannot be generally
compensated although in current process these variations are
very small fraction and hence negligible. Thus, we achieve a
highly stable and invariant current source. The performance of
the current reference is listed in Table 5.
DC Power 427.3µW
Temp
Coefficient 2.14ppm/deg C
IREF-HIGH 26.4 uA (only resistor)
IREF-LOW 17.54 uA (only resistor)
Table 5. Current Reference Specification
IV. SIMULATION RESULTS
The delta-sigma ADC calibration bits were set to 3'b000 for
a reference current equal to 12.3nA and integrator capacitance
of 1pF for maximizing the resolution to 100pA of input
current. The ADC was also tested for a calibration setting of
3'b111 fixing the reference current at 1.31uA and integrator
capacitor 10.9 pF for an input current of 1.5uA. The sampling
frequency of the ADC loop is fixed at 130 KHz and the
resultant simulation waveforms indicate the ADC is able to
support a dynamic range of 100pA-1.5uA. Simulation results
for the two extremes of the input current are shown in fig25-
fig29.
432
434
436
438
440
442
-15 -10 -5 0 5 10 15
Fre
quen
cy i
n M
Hz
Supply Voltage variation in %
Frequency Pushing
+−=∆
sFW
FW
RR
RVssVddVcell )(max
)(22
2
FWsFW
FW
RRRA
RA
Vsrc
Vcell
++=
Figure 19. Potentiostat- Chemical Sensor
Interfacing Circuit
Figure 21. Input Signal of 1nA @ 100 Hz
Figure 22. Spectrum of the Sigma Delta at ADC Output
Figure 23. Spectrum of the Decimated Output Signal
Chemical Sensor
Figure 20. Operational Amplifier Input referred Noise Characteristics
. Input Signal of 1nA @ 100 Hz
This work
∆∑ Modulator
Sampling rate
0.13 MHz
Input Current
Range
600 nA
Current Resolution 100 pA
Communication
Scheme
FSK @ 433 MHz
RF Data
Transmission rate
0.26 Mbps
Power Supply 3.3 V
Power
Consumption
Sensor
RF Transmistter
330 uW
1 mW
Technology 0.5 um CMOS
Table 8. Performance Summary
. Spectrum of the Sigma Delta at ADC Output
. Spectrum of the Decimated Output Signal
Figure 24. Full Chip Layout
0.00E+00
5.00E-09
1.00E-08
1.50E-08
2.00E-08
2.50E-08
3.00E-08
3.50E-08
4.00E-08
4.50E-08
0 200 400 600
Inp
ut
refe
rre
d n
ois
e i
n
V/s
qrt
(Hz)
Frequency in Hz
. Operational Amplifier Input referred Noise Characteristics
This work [1]
0.13 MHz 0.13 MHz
600 nA 450 nA
100 pA 132 pA
FSK @ 433 MHz
0.26 Mbps 0.26 Mbps
2.5 V
330 uW
57 uW
1 mW
0.5 um CMOS 0.5 um CMOS
Performance Summary
. Full Chip Layout
800 1000 1200
Frequency in Hz
Figure 25 Input Current Signal of 100pA
Figure 26 Decimated Output for a 100pA sinusoidal input
Figure 27 Input Current Signal of 1.5uA
Figure 28 Decimated Output for a 100pA sinusoidal input
Figure 29 ADC output for a 1.5uA input current sinusoid
-1.50E-10
-1.00E-10
-5.00E-11
0.00E+00
5.00E-11
1.00E-10
1.50E-10
0.00E+005.00E-031.00E-021.50E-022.00E-022.50E-02
Input Current
-8.80E-04
-8.60E-04
-8.40E-04
-8.20E-04
-8.00E-04
-7.80E-04
-7.60E-04
-7.40E-04
0.00E+005.00E-031.00E-021.50E-022.00E-022.50E-02
Decimated Output
filter
10 per. Mov.
Avg. (filter)
-0.000002
-1.5E-06
-0.000001
-5E-07
0
0.0000005
0.000001
0.0000015
0.000002
0 0.005 0.01 0.015 0.02
Input Current
-0.006
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0 0.005 0.01 0.015
Decimated Output
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018
ADC digitized output for a 1.5uA input current
V. TESTING & CALIBRATION
Test Signal Generator
The test signal generator has been created to calibrate the
ADC loop. It accepts an input current and scales it to four
different versions 10,20,40,80 percent of the input current.
With the help of a 2 to 4 decoder it is possible to generate
different values of input current as required. For example with
a 1uA input current to this circuit current in the range of 0.1 to
1.5 uA in various binary weighted steps can be generated.
X1 X2 X3 X4 Iout
1 0 0 0 100 nA
0 1 0 0 200 nA
0 0 1 0 400 nA
0 0 0 1 800 nA
Table 6. Current Selection using Digital Logic.
Current Source / Sink Scaling circuit
A scaling circuit has been implemented for scaling the
reference current used in the Current Steering DAC block.
This circuit generates currents for the DAC and its biasing
OTAs. Common-centroid technique has been used in layout to
achieve current matching. The scaling is controlled by a 3-bit
digital interface employing a 3:8 bit decoder which binary
scales the reference currents from 11.2nA-1.2uA. For a list of
reference currents for different calibration inputs values refer
table 6.
Capacitive Bank
The capacitive bank sits over the Integrator whose value
must be chosen according to the Dynamic range of the input
current. The same digital inputs that scale the DAC reference
current are reused here. The selection logic is given in table 7.
Encoder
Select Logic
Capacitor Input
Current
000 1 pF 11.2 nA
001 1.1 pF 25 nA
010 1.4 pF 50 nA
011 1.9 pF 100 nA
100 2.9 pF 164 nA
101 4.9 pF 320 nA
110 8.9 pF 640 nA
111 10.9 pF 1.2 uA
Table 7. Calibration settings
Calibration Procedure
Using an external precision current generator, a
known input signal is fed to the test signal generator. The
current value required is selected by digital control of the Test
signal generator and applied to the ADC loop. The Current
DAC in the loop and integrator’s capacitance are chosen
through the digital combination to ensure optimum results.
Testing Procedure
For the input sensing current range, the optimum
DAC reference current and Integrator capacitor have been
selected, as part of the calibration cycle. The complete testing
procedure involves sensing the chemical sensor input,
converting that into digital data using the ADC and wirelessly
transmitting the Encoded signal using FSK modulation. At the
receiving end an external FSK demodulator will demodulate
the RF signal into a digital stream of 1’s and 0’s. The digital
data is then post-processed in MATLAB using Digital
Decimation to recover the input signal. This digital data is also
used for generating the Sigma-Delta ADC figure of merits.
The overall layout has been tailored in such a way
that the complete system can be decoupled into three different
blocks. The three-terminal chemical sensor interface, Sigma
Delta ADC & VCO can be characterized separately.
Additional pads are used to take output from all important
nodes on the chip to facilitate testing. Probe pad structures
have also been inserted at numerous places to aid debug.
VI. MEASUREMENT RESULTS
The characterization of chemical sensor is divided into three
parts. The testing of the Sigma delta analog to digital
converter, VCO and Potentiostat are performed separately to
characterize them. As the chip has the full lineup of the
chemical sensor, the VCO output basically gives the output of
the complete system. The potentiostat was characterized by
varying the reference electrode and source voltage. The cell
voltage is obtained as a function of source and reference
electrode voltage. The plot of Vsrc versus Vcell Fig 30 when
compared with Fig 19, shows a very close resemblance to
what was expected. The sigma delta modulator was tested by
applying a constant input current. The reference current for the
DAC was setup and the corresponding output waveform was
observed. The plot of ADC’s time domain output and
spectrum is given in Fig 31 and 32 respectively. The reference
current was set at approximately 50 nA. The integration
capacitor is set to 2.3 pF. From this setting the minimum
current that can be detected is 18 nA. The output spectrum in
Fig 32 indicates the ADC output contains tones at 60 Hz and
multiples. This appears because of supply coupling and
absence of anti-aliasing filter at signal input. The VCO output
exhibits a drift of 18 MHz from the expected frequency of 433
MHz. The reason for drift is the effect of wire bond
inductance and parasitic capacitance involved in the overall
design. To reduce the drift the inductance value should be
reduced from 65nH to 56 nH. The performance summary of
the VCO is given in the Table 8. The performance summary of
the chemical sensor is given below. The overall power
consumption is vastly different from previously estimated
values because of amount of current necessary to provide a
330 mV Vpp voltage swing across 50 ohms load.
Parameters Measured results Simulation results
∆Σ Modulator
Sampling rate 130 KHz 130 KHz
Minimum
Input Current 18 nA @ 120 Hz 11 nA @ 120 Hz
Current
resolution NA 132 pA
Communication
Scheme FSK:415/412 MHz FSK:433/430 MHz
Output Power -1.2 dBm 0 dBm
Power Supply 3.3 V 3.3 V
Power
Consumption 1.33 mA 4.75 mA
Table 9. Performance summary of Chemical sensor
VII. CONCLUSION
In this paper we proposed a bio-chemical sensor circuit
based on amperometry. A current input ∆-∑ Analog to Digital
converter, FSK based 433MHz RF transmitter and potentiostat
are implemented in AMI 0.5um process. The system aims to
monitor bio-chemical phenomenon generating currents that
range from a few hundred pico-amperes to a few micro-
amperes. The RF transmitter enables walk-in access type
portability to the sensor interface.
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Cyclic Voltammetry,” IEEE Transactions on Biomedical Circuits and
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Figure 30 DC Characterization of the Potentiostat.
Fig 31 ADC time domain output
Fig 32 ADC Output Spectrum
Selection Logic VCO Frequency Power Supply VCO Frequency
MHz V MHz
000 416.3 / 419.5 3.0 426.3
001 411.8 / 419.5 3.1 422.2
010 408.7 / 419.5 3.2 418.7
011 405.3 / 419.5 3.3 416.3
100 401.8 / 419.5 3.4 415.2
101 398.6 / 419.5 3.5 415.3
3.6 415.2
Table 8. VCO Performance Summary
-1.5
-1
-0.5
0
0.5
1
1.5
-2 -1 0 1 2 3
Vce
ll in
Vo
lts
Vsrc in Volts
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