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UC Berkeley, Dept of EECSEE141, Fall 2005, Project 2
Speed-Area Optimized 8-Bit Adder
Presentation Slides
EE141 – Project 2 2
Critical Path Analysis
Critical Path: A: (00000000 > 10101010) B: (00000000 > 11010101) Cin: (0 > 0)
tcritical tsetup 2tcarry 4 tmux
EE141 – Project 2 3
Critical Path AnalysisSetup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Setup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Setup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Setup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Setup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Setup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Setup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Setup –AxorB, P, G
0 Carry precompute
1 Carry precompute
Dynamic Multiplexer
Sum Generation
Critical Path indicated by Critical transition: A = 10110111; B=01001001; Cin = 1:Carry
generated in the first bit and then ripples through the Multiplexers holding the precomputed values until it reaches the final sum stage and generates sum8. These Inputs ensure that sum 8 has to wait for Carry_out_7 to reach it for the sum to be valid.
Critical path equation : tcritical = tsetup + 2tcarry + 4tmux + tsum.
EE141 – Project 2 4
Sizing Characteristics
To Carryout
EE141 – Project 2 5
Sizing Optimization
16X
Stage Z: LE=1 B=1
3
3.84u/1.92u
960n
960n
2.88u/720n
2.4u/1.2u
0.96n0.96n1.2u 0.96n
0.48u
0.48u
16XGin7Gin5Gin0 Gin1 Gin2 Gin3 Gin4 Gin6
Pin7Pin1 Pin2 Pin5Pin3 Pin4 Pin6
Pin0
A
Stage V: LE=1, B=1
Stage W: LE=1, B=4
Stage X : LE=4/3, B=1
Stage Y: LE=2, B=1
Area Concern
0.96u/0.48u
163
812
3
411
FO
LE
8.24163
8
4:5/1
5/1
PE
Branching 00.1v78.2w 08.4y
70.5z
94.1xSize: 2.
5
4
2.5
Manchester Sizing
EE141 – Project 2 6
Dynamic Functionality Check
0 0 0
0 1 0
0 0 0
0 0 0
0 1 0
0 0 0
0 0 0
0 0 1
0 1 0
EE141 – Project 2 7
Static Functionality Check
S0
S1
S2
S3
S4
S5
S6
S7
Cout
EE141 – Project 2 8
Layout Techniques
Size : 1265.22 m2
(33.00m x 38.34m)
Critical Path drawn in arrow
Aspect Ratio = 1.162
Routing• Metal 1
− Horizontal Line− VDD, GND
• Metal 2:− Vertical Line
• Metal 3:− Clock Signals
FA0 FA1 FA2 FA3
FA7 FA6 FA5 FA4
INPUT BUFFER INPUT BUFFER
INPUT BUFFER INPUT BUFFER
OUTPUTBUFFER
OUTPUTBUFFER
OUTPUTBUFFER
OUTPUTBUFFER
CLOCKCHAIN
EE141 – Project 2 9
First Stage (2 bits)
Third Stage (2 bits)
Last Bit (1 bit)
Outputs (Buffers)
Second Stage (3 bits)
Byp
ass
Mu
x
Cout<1>
Cout<6>
B<0>
A<0>
P<0>Cout<0>
Cmuxout (“Cout<4>”)
Cout<5>
S<7>
Layout Techniques
EE141 – Project 2 10
Layout Techniques
FA 2
FA 1
Buffer
FA 3
FA 4Buffer
FA 6
FA 5
Buffer
FA 7
FA 8Buffer
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