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The Continued Evolution of Re-Configurable FPGAs for
Aerospace and Defense Strategic Applications
Howard Bogrow
Bogrow 2 MAPLD 2005/176
AbstractPresent and future aerospace and defense applications continue to demand ever increasing performance, density, and above all flexibility from FPGAs. The Virtex families of re-configurable FPGAs provide the technology to meet these demands. Various members of these families are currently available in both COTs and SMD formats, as well as in radiation tolerant versions. Xilinx is also fully supporting a recently announced software tool that automates the implementation of TMR (Triple Modular Redundancy) into members of these FPGA families for mission critical applications. Xilinx has received government funding towards the development of a Single Event Immune Re-configurable FPGA (SIRF) with possibly strategic performance. This paper will focus on Xilinx currently available Virtex solutions, while also discussing Xilinx's future development efforts. There will also be some discussion of the various manufacturing flows utilized by Xilinx to address the stringent requirements of current and future space missions, as well as the latest package developments.
Bogrow 3 MAPLD 2005/176
1985 1990 1995 2000 2005
Xilinx Long-Term Commitment to Aerospace & Defense
Source: Company reports
Xilinx Founded
Introduced 1st field programmable gate array (FPGA)
1st device qualified to MIL-STD-883
1st Standard Military Drawing (SMD) released
ISO 9002 certification
1st 0.35 & 0.25m FPGAs QML & ISO9001 certifications
Virtex million-gate FPGAs1st rad tolerant devices
1st 150nm Virtex-II Platform FPGARad tolerant Virtex & SPROMs
1st 130nm Virtex-II ProSEE Consortium formed
1st 90nm Virtex-4 Platform FPGARad tolerant Virtex-II Pro
84
8589
91
95
97
98
00
02
04
Xilinx on Mars
Bogrow 4 MAPLD 2005/176
19991999 20002000 20022002 20032003 20042004 20052005
65 nm65 nm
90 nm90 nm
130 nm130 nm
150 nm150 nm
180 nm180 nm
45 nm45 nm
20012001
1 year Technology Leadership1 year Technology Leadership
First to 90 nmFirst to 300 mm
SIA Roadmap
SIA Roadmap
Xilinx Technology Roadmap• Leading SIA Roadmap
– 150nm, 130nm and 90nm– 300mm wafers starting with Virtex-II
and Virtex-E• First 90nm Spartan-3 family in full
production• First Virtex-4 devices now shipping
Virtex-EExtended Memory
Virtex-II
Virtex-IIPRO
Spartan-3Virtex-4
Bogrow 5 MAPLD 2005/176
Aerospace and DefenseVirtex Mil Spec Products
2003 2004 2005 2006
220nm
180nm
150nm
130nm
90nm
65nm
Mil-Temp Space Grades
Rad Tolerant
Next GenerationNext GenerationNext GenerationNext Generation
Mil-Temp Space Grades
“Rad by Design” Program
Mil-Temp Space Grades
Virtex-II
Virtex-IIPRO
Virtex-4
Bogrow 6 MAPLD 2005/176
Aerospace and Defense Qualifications
Closing the Gap with CommercialYears from Commercial Production
Qualification
4
XC3000XQ4000XL
3
2
1
XC4000 XC4000E XQ4000EX
XQ4000XL
Virtex
Virtex Virtex-E
Virtex-II
Virtex-II
Virtex-II Pro
Virtex-II Pro
Space Qualification
Military Qualification
Program Goals
FPGA Family Generations
Virtex-4
Virtex-4
RadHard ByDesign ProgramVirtex-E
Bogrow 7 MAPLD 2005/176
Virtex-4 ASMBL™ ColumnarArchitecture
• Virtex 4th Generation advanced FPGA architecture
• Enables “dial-In” resource allocation mix
–Logic, DSP, BRAM, I/O, MGT,DCM, PowerPC
• Enabled by Flip-Chippackaging technology
– I/O columns distributed throughout the device
Bogrow 8 MAPLD 2005/176
Three Virtex-4 Platforms
ResourceResource
14-200K LCs14-200K LCsLogic
Memory
DCMs
DSP Slices
SelectIO
RocketIO
PowerPC
Ethernet MAC
LXLX FXFX SXSX
0.9-6Mb0.9-6Mb
4-124-12
32-9632-96
240-960240-960
23-55K LCs23-55K LCs
2.3-5.7Mb2.3-5.7Mb
4-84-8
128-512128-512
320-640320-640
12-140K LCs12-140K LCs
0.6-10Mb0.6-10Mb
4-204-20
32-19232-192
240-896240-896
0-24 Channels0-24 Channels
1 or 2 Cores1 or 2 Cores
2 or 4 Cores2 or 4 Cores
N/A
N/A
N/A
N/A
N/A
N/A
Density Processor Cores DSP
Bogrow 9 MAPLD 2005/176
Process Technology Advances
• Advanced 90-nm process
• 11-Layer metallization
– 10 copper + 1 aluminum
• New Triple-Oxide Structures
– Lower quiescent power consumption
• Benefits:
– Best cost
– Highest performance
– Lowest power
– Highest density
• Over 1 million 90 nm FPGAs shipped
Channel
GateGate
SourceSource DrainDrain
SourceSource
MetalMetal
ConnectionConnection
DrainDrain
MetalMetal
ConnectionConnection
Bogrow 10 MAPLD 2005/176
Dramatic Power Reduction in Virtex-4
Frequency
Power Consumption
50%130 nm FPGAs
Virtex-4 cuts power by 50%• Measured 40% lower static power with
Triple-Oxide technology• 50% lower dynamic power with 90-nm
• Lower core voltage• Less capacitance
• Up to 10x lower dynamic power with hard IP• Integration means fewer transistors per function
ChallengesChallenges- Static power grows with process generations
- Transistor leakage current- Dynamic power grows with frequency
- P = cv2f
ChallengesChallenges- Static power grows with process generations
- Transistor leakage current- Dynamic power grows with frequency
- P = cv2f
Bogrow 11 MAPLD 2005/176
Virtex-4 Configuration Features
• Higher configuration speed – 100MHz Serial & Parallel interface– 66MHz JTAG interface
• CCLK available to users• 256 bit AES security• Configuration ECC• ICAP and DRP support• Dedicated configuration I/O bank• Enhanced partial reconfiguration• Compatible with previous FPGAs
• Supports earlier configuration modes
CCLKCCLK
DINDIN
CS_BCS_BRDWR_BRDWR_B
PROG_BPROG_B
TCKTCKTDITDITMSTMS
TDOTDO
D[7:0]D[7:0]DOUT_BUSDOUT_BUS
YY
DONEDONE
INITINIT
MODE[2:0]MODE[2:0]
Bogrow 12 MAPLD 2005/176
FPGA Radiation ToleranceTID Trends vs Product/Technology
0
50
100
150
200
250
300
350
400
50100150200250300350nm
TID
Kra
ds
(Si)
(per
101
9.5)
Process trends*:• Gate oxide continues to thin• Oxide tunnel currents increase• Gate stress voltage decreases
*See “CMOS SCALING, DESIGN PRINCIPLES and HARDENING-BY-DESIGN METHODOLOGIES” by Ron Lacoe, Aerospace Corp2003 IEEE NSREC Short Course 2003
• 350nm - XQ4000XL – 60 krad (Si)
• 220nm - XQVR (Virtex)– 100 krad (Si)
• 150nm - XQR2V (Virtex-II)– 200 krad (Si)
• 130nm – XQR2VP– 250 krad (Si)
• 90nm (Preliminary)– 300 krad (Si)
Bogrow 13 MAPLD 2005/176
SEE Consortium Platform FPGA Test Phases
Static(1Q05)
Dynamic (2Q05)
Mitigation (3Q05)
V-2pro
Multi-GigabitSerial Transceivers
PowerPC Processor & IP
FPGA Fabric and Static Cells
• Parallel Test Approach to accelerate product qualification
• 3 SEE Consortium Tiger Teams: Fabric, Processor, Serial Transceiver
Special Solutions
V-2pro
V-2pro
V-4
V-4
V-4
Bogrow 14 MAPLD 2005/176
Dose Rate Testing• Historical Testing
– XC4036XL• Testing was done by Lockheed• Testing range of 1.0E7 to 4.0E11
(20 nsec pulse) tested• No data upset >1.3E9 to >3.0E9 • No latch-up beyond 4.0E11
– XCVR300E• Testing done by ITT (MRC)• Testing range of 6.3E7 to 3.0E9• No upset until > 4.0E8 (non-epi) to
>1.0E9 (epi)• No latch-up beyond 3.0E9
• Current Test Program– XC2VP40
• Work is funded by MDA• Testing is being done by a consortium
consisting of AFRL, Crane, Xilinx and Raytheon
• Initial tests were run July 2004 at Navsea Crane using 60 MeV electron beam source utilized commercial Virtex-IIpro performance board and commercial V-IIpro parts
• Tests to compare RH (epi) performed in November 2004 at Navsea Crane
• No upset until > 3.0E8 • RH (epi) no POR until >1.0E9• No Latch-up through >1.0E10
Bogrow 15 MAPLD 2005/176
• Software development tool to automatically implement TMR customer designs optimized for Xilinx FPGAs
• Result of Xilinx/Sandia National Labs partnership– Released to Production in Sept 2004
• Support all design entry methods and HLLs– NGO & NGC based input– EDIF based output
• OS Support– Windows 2000/XP GUI Support– Windows/UNIX PERL Command Line Support
• Supports ISE 5.2i, 6.1i, 6.2i
TMRTool
Bogrow 16 MAPLD 2005/176
Xilinx Design Flow
Design Entry(Verilog, VHDL, Schematics)
FunctionalSimulation
TimingSimulation
Design Verification
Synthesis(XST, Synplify, …)
Implementation
PAR
Translate
Map
Download
Static TimingAnalysis
TMRTool Netlist Flow
XST
NGCNGC
NGDBUILDXTMR
EDIFEDIF
NGONGO
EDIF TMREDIF TMR
EDA & CORE
(Translate)
Third Party EDA and Core Tools
• Design entry tools and core generators write out EDIF for FPGA implementation
• EDIF files are translated to NGO files by ngdbuild.exe
Xilinx Synthesis Tool
• XST writes out one NGC for everything synthesized
TMR Generated Design
• TMRTool reads in NGO and NGC files and writes out a single EDIF file for the TMR design
• A new implementation project is created with this new source file.
Bogrow 17 MAPLD 2005/176
RocketIO™Multi-Gigabit Transceiver
Block Memory
Clocking & Clock Mgmt
PowerPC™
Configuration Memory
Control Logic
Logic FabricDSP Fabric
Virtex-4Silicon Floorplan
SelectIO
Phase-1: Design Feasibility, Test Chip
Phase-2: Chip Development
Phase-2A: Advanced Features
RadHard by Design ProgramSEU Immune Reconfigurable FPGA (SIRF)
Bogrow 18 MAPLD 2005/176
SIRF Radiation Goals
Total Dose > 300 krad(Si) (requirement) > 1 Mrad(Si) (goal)
Dose Rate Latch up > 11010 rad(Si)/sec
Upset > 1109 rad(Si)/sec (requirement) > 5109 rad(Si)/sec (goal)
SEE Latch up none up to LET > 100 MeV-cm2/mg Upset threshold LET > 40 MeV-cm2/mg,
error rate < 110-10 errors/bit-day (requirement) threshold LET > 100 MeV-cm2/mg,
error rate < 110-10 errors/bit-day (goal) Functional threshold LET > 40 MeV-cm2/mg, Interrupt error rate < 110-10 errors/bit-day (requirement) threshold LET > 100 MeV-cm2/mg,
error rate < 110-10 errors/bit-day (goal)
Bogrow 19 MAPLD 2005/176
• CG717CG717
o 35 x 35mm body, 1.27mm pitch, cavity-up
o Footprint compatible with the BG728
o Developed for the 2V3000
o Wire Bond, gold
o Au-Sn lid (hermetically sealed)
• CF1144CF1144
o 35 x 35mm body, 1.00mm pitch
o Footprint compatible with the FF1152
o Developed for the 2V6000
o Flipchip with high lead balls, MSL1
Advanced Packaging
Bogrow 20 MAPLD 2005/176
Enhanced Flow – In DevelopmentHermetic Wire Bond Ceramic Flip Chip
Mask set control X XTraceability X XWafer Lot Acceptance X XNon-destructive bond pull X Flip chip equivalentInternal visual X XConstant acceleration X Flip chip equivalentPIND X N/ASerialization X XPre burn-in electrical X XStatic burn in X XPost burn-in electrical X XDelta calculations X XPDA X XDynamic burn-in X XPost burn-in electrical X XDelta calculations X XPDA X XFinal electrical X XX-ray X N/AExternal Visual X XGroup A X XGroup B X Flip chip equivalentGroup C X XGroup D X Flip chip equivalentGroup E X XData summary X X
Bogrow 21 MAPLD 2005/176
Summary• Virtex-4 architecture and design methodology enables
rapid development of Platform-specific FPGAs with embedded cores
• Advances in 90nm chip design resulted in optimized performance, lower power, and first-silicon success of Virtex-4
• SEE Consortium primary vehicle for radiation characterization testing (US and European)
• Rad Tolerant program will continue with concurrent phase-in of Rad Hard by Design program
• Advanced packaging and enhanced process flows integral part of overall development efforts
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